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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/107185] [13 Regression] during RTL pass: vregs ICE: in
 extract_insn, at recog.cc:2791 (unrecognizable insn) with -ffast-math and
 lrintf()
Date: Tue, 11 Oct 2022 13:58:35 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D107185

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:b65945e7fb8d0f6cf911d371926d25e7ea82db62

commit r13-3232-gb65945e7fb8d0f6cf911d371926d25e7ea82db62
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Oct 11 15:57:09 2022 +0200

    i386: Fix up RTL checking ICE [PR107185]

    On Tue, Oct 11, 2022 at 04:03:16PM +0800, liuhongt via Gcc-patches wrot=
e:
    > gcc/ChangeLog:
    >
    >       * config/i386/i386.md (*notxor<mode>_1): New post_reload
    >       define_insn_and_split.
    >       (*notxorqi_1): Ditto.

    > --- a/gcc/config/i386/i386.md
    > +++ b/gcc/config/i386/i386.md
    > @@ -10826,6 +10826,39 @@ (define_insn "*<code><mode>_1"
    >     (set_attr "type" "alu, alu, msklog")
    >     (set_attr "mode" "<MODE>")])
    >
    > +(define_insn_and_split "*notxor<mode>_1"
    > +  [(set (match_operand:SWI248 0 "nonimmediate_operand" "=3Drm,r,?k")
    > +     (not:SWI248
    > +       (xor:SWI248
    > +         (match_operand:SWI248 1 "nonimmediate_operand" "%0,0,k")
    > +         (match_operand:SWI248 2 "<general_operand>" "r<i>,<m>,k"))))
    > +   (clobber (reg:CC FLAGS_REG))]
    > +  "ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
    > +  "#"
    > +  "&& reload_completed"
    > +  [(parallel
    > +    [(set (match_dup 0)
    > +       (xor:SWI248 (match_dup 1) (match_dup 2)))
    > +     (clobber (reg:CC FLAGS_REG))])
    > +   (set (match_dup 0)
    > +     (not:SWI248 (match_dup 1)))]
    > +{
    > +  if (MASK_REGNO_P (REGNO (operands[0])))

    This causes --enable-checking=3Dyes,rtl,extra regression on
    gcc.dg/store_merging_13.c test on x86_64-linux:
    .../gcc/testsuite/gcc.dg/store_merging_13.c: In function 'f13':
    .../gcc/testsuite/gcc.dg/store_merging_13.c:189:1: internal compiler er=
ror:
RTL check: expected code 'reg', have 'mem' in rhs_regno, at rtl.h:1932
    0x7b0c8f rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, =
int,
char const*)
            ../../gcc/rtl.cc:916
    0x8e74be rhs_regno
            ../../gcc/rtl.h:1932
    0x9785fd rhs_regno
            ./genrtl.h:120
    0x9785fd gen_split_260(rtx_insn*, rtx_def**)
            ../../gcc/config/i386/i386.md:10846
    0x23596dc split_insns(rtx_def*, rtx_insn*)
            ../../gcc/config/i386/i386.md:16392
    0xfccd5a try_split(rtx_def*, rtx_insn*, int)
            ../../gcc/emit-rtl.cc:3799
    0x132e9d8 split_insn
            ../../gcc/recog.cc:3384
    0x13359d5 split_all_insns()
            ../../gcc/recog.cc:3488
    0x1335ae8 execute
            ../../gcc/recog.cc:4412
    Please submit a full bug report, with preprocessed source (by using
-freport-bug).
    Please include the complete backtrace with any bug report.
    See <https://gcc.gnu.org/bugs/> for instructions.

    Fixed thusly.

    2022-10-11  Jakub Jelinek  <jakub@redhat.com>

            PR target/107185
            * config/i386/i386.md (*notxor<mode>_1): Use MASK_REG_P (x) ins=
tead
of
            MASK_REGNO_P (REGNO (x)).=