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From: "linkw at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug testsuite/107240] [13 Regression] FAIL:
 gcc.dg/vect/vect-bitfield-write-2.c since r13-3219-g25413fdb2ac249
Date: Mon, 17 Oct 2022 06:21:01 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D107240

--- Comment #7 from Kewen Lin <linkw at gcc dot gnu.org> ---
Well, it does helps vect-bitfield-write-{2,3}.c, but it doesn't help
vect-bitfield-write-{2,3,4}.c since they do require vector/vector shift
supports.

I guess it might be a good idea to add the vect_long_long effective target
requirement for these relevant test cases.  For now, I don't see we make it
effective for powerpc*-*-*, if no objections I'm going to test=20

diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index fdd88e6a516..29d7b4ebd15 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7059,7 +7059,9 @@ proc check_effective_target_vect_long_long { } {
              || ([istarget mips*-*-*]
                  && [et-is-effective-target mips_msa])
              || ([istarget s390*-*-*]
-                 && [check_effective_target_s390_vx]) }}]
+                 && [check_effective_target_s390_vx])
+             || ([istarget powerpc*-*-*]
+                 && [check_effective_target_has_arch_pwr8]) }}]
 }

Although it's not that accurate, as we can have V2DI vector load/store and =
some
operations like bitwise on power7, it's only for testing and the missing sc=
ope
is very limited.=