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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/107261] ICE: in classify_argument, at
 config/i386/i386.cc:2523 on __bf16 vect argument or return value
Date: Mon, 31 Oct 2022 01:50:56 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D107261

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:6913cad2a38bc406b137b06d579b650f6fe9a2e6

commit r13-3565-g6913cad2a38bc406b137b06d579b650f6fe9a2e6
Author: liuhongt <hongtao.liu@intel.com>
Date:   Tue Oct 25 13:31:54 2022 +0800

    Enable V4BFmode and V2BFmode.

    Enable V4BFmode and V2BFmode with the same ABI as V4HFmode and
    V2HFmode. No real operation is supported for them except for movement.
    This should solve PR target/107261.

    Also I notice there's redundancy in VALID_AVX512FP16_REG_MODE, and
    remove V2BFmode remove it.

    gcc/ChangeLog:

            PR target/107261
            * config/i386/i386-modes.def (VECTOR_MODE): Support V2BFmode.
            * config/i386/i386.cc (classify_argument): Handle V4BFmode and
            V2BFmode.
            (ix86_convert_const_vector_to_integer): Ditto.
            * config/i386/i386.h (VALID_AVX512FP16_REG_MODE): Remove
            V2BFmode.
            (VALID_SSE2_REG_MODE): Add V4BFmode and V2BFmode.
            (VALID_MMX_REG_MODE): Add V4BFmode.
            * config/i386/i386.md (mode): Add V4BF and V2BF.
            (MODE_SIZE): Ditto.
            * config/i386/mmx.md (MMXMODE) Add V4BF.
            (V_32): Add V2BF.
            (V_16_32_64): Add V4BF and V2BF.
            (mmxinsnmode): Add V4BF and V2BF.
            (*mov<mode>_internal): Hanlde V4BFmode and V2BFmode.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr107261.c: New test.=