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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/107540] [13 Regression] ICE: SIGSEGV in memory_operand(rtx_def*, machine_mode) (recog.cc:1834) with -flive-range-shrinkage
Date: Wed, 09 Nov 2022 01:13:19 +0000	[thread overview]
Message-ID: <bug-107540-4-br7v7ycWZJ@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-107540-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107540

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:916bec9a05ea522c81381e0c93590d46965d9c7b

commit r13-3821-g916bec9a05ea522c81381e0c93590d46965d9c7b
Author: liuhongt <hongtao.liu@intel.com>
Date:   Mon Nov 7 09:55:25 2022 +0800

    Fix incorrect insn type to avoid ICE in memory attr auto-detection.

    Memory attribute auto detection will check operand 2 for type sselog,
    and check operand 1 for type sselog1. For below 2 insns, there's no
    operand 2. Change type to sselog1.

    gcc/ChangeLog:

            PR target/107540
            * config/i386/sse.md (avx512f_movddup512<mask_name>): Change
            type from sselog to sselog1.
            (avx_movddup256<mask_name>): Ditto.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr107540.c: New test.

  parent reply	other threads:[~2022-11-09  1:13 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-06  8:28 [Bug target/107540] New: " zsojka at seznam dot cz
2022-11-06 18:33 ` [Bug target/107540] " pinskia at gcc dot gnu.org
2022-11-07  1:39 ` crazylht at gmail dot com
2022-11-07  2:02 ` crazylht at gmail dot com
2022-11-09  1:13 ` cvs-commit at gcc dot gnu.org [this message]
2022-11-09  1:14 ` crazylht at gmail dot com
2022-11-21 11:59 ` marxin at gcc dot gnu.org

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