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From: "crazylht at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/107546] [10/11/12/13 Regression] simd, redundant pcmpeqb
 and pxor
Date: Mon, 07 Nov 2022 08:27:47 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D107546

--- Comment #7 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Hongtao.liu from comment #3)
> Failed to match this instruction:
> (set (reg:V16QI 95)
>     (eq:V16QI (gt:V16QI (subreg:V16QI (reg:V2DI 89 [ MEM[(const __m128i_u=
 *
> {ref-all})p_2(D)] ]) 0)
>             (mem/u/c:V16QI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0  S16
> A128]))
>         (const_vector:V16QI [
>                 (const_int 0 [0]) repeated x16
>             ])))
>=20
>=20
> I think rtl can simplify vector comparison
>=20
> (eq (gt op1 op2) const0_rtx) to just (gt op2 op1).

No, it's not, it's (le op1 op2) which is not supported under sse2 ,and this=
 is
the exact reason we do negate the result in the backend.=