From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 54BC53858D3C; Tue, 8 Nov 2022 08:28:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 54BC53858D3C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1667896125; bh=VOevtOu3/lrct7ukUgSJ9MfNs4v6JEIXodhnQ7irpfw=; h=From:To:Subject:Date:In-Reply-To:References:From; b=x2Nmp63H120g+404y9kb26a7H6d95l8LdsLzkrPRBT5ynR4wpYwoRiaLjWX5irxFn MJTYeHwb9LPNvMzn+1holozSnSzi2T3BupxvJKPgJZ3Tmx6a2UNuoBo6VnlhUd+t59 HX74eztq17b7VmOdhLR+KbZA4pgkoKyGAzMUsKuk= From: "crazylht at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/107563] __builtin_shufflevector fails to pshufd instructions under default x86_64 compilation toggle which is the sse2 one Date: Tue, 08 Nov 2022 08:28:44 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: crazylht at gmail dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D107563 --- Comment #10 from Hongtao.liu --- (In reply to cqwrteur from comment #9) > (In reply to cqwrteur from comment #8) > > for sse2 to do the __builtin_convertvector job yeah >=20 > https://godbolt.org/z/dsf3WK58E >=20 > using temp_vec_type [[__gnu__::__vector_size__ (16)]] =3D char; > void foo4(temp_vec_type& v) noexcept > { > v=3D__builtin_shufflevector(v,v,1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14); > } >=20 > This is even more interesting. >=20 > foo4(char __vector(16)&): # @foo4(char __vector(16)&) > movdqa (%rdi), %xmm0 > movdqa %xmm0, %xmm1 > psrlw $8, %xmm1 > psllw $8, %xmm0 > por %xmm1, %xmm0 > movdqa %xmm0, (%rdi) > retq >=20 > clang generates this. by using ror and or This is interesting case, similar for psrld/psrlq + pslld/psllq + or.=