[Bug target/107671] New: i386: Missed optimization: use of bt in bit test pattern when LHS is an array index

[Bug target/107671] New: i386: Missed optimization: use of bt in bit test pattern when LHS is an array index

[ibuclaw at gdcproject dot org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107671

            Bug ID: 107671
           Summary: i386: Missed optimization: use of bt in bit test
                    pattern when LHS is an array index
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ibuclaw at gdcproject dot org
  Target Milestone: ---

int bt32_setb(const __UINT32_TYPE__ *p, __UINT32_TYPE__ bitnum)
{
    return ((p[bitnum >> 5] & (1  << (bitnum & 31)))) != 0;
}

int bt64_setb(const __UINT64_TYPE__ *p, __UINT64_TYPE__ bitnum)
{
    return ((p[bitnum >> 6] & (1L << (bitnum & 63)))) != 0;
}

int bt32_setb2(const __UINT32_TYPE__ *p, __UINT32_TYPE__ bitnum)
{
    return (p[bitnum >> 5] >> (bitnum & 31)) & 1;
}

int bt64_setb2(const __UINT64_TYPE__ *p, __UINT64_TYPE__ bitnum)
{
    return (p[bitnum >> 6] >> (bitnum & 63)) & 1;
}

int bt32_setae(const __UINT32_TYPE__ *p, __UINT32_TYPE__ bitnum)
{
    return ((p[bitnum >> 5] & (1  << (bitnum & 31)))) == 0;
}

int bt64_setae(const __UINT64_TYPE__ *p, __UINT64_TYPE__ bitnum)
{
    return ((p[bitnum >> 6] & (1L << (bitnum & 63)))) == 0;
}

int bt32_setae2(const __UINT32_TYPE__ *p, __UINT32_TYPE__ bitnum)
{
    return !((p[bitnum >> 5] >> (bitnum & 31)) & 1);
}

int bt64_setae2(const __UINT64_TYPE__ *p, __UINT64_TYPE__ bitnum)
{
    return !((p[bitnum >> 6] >> (bitnum & 63)) & 1);
}

[Bug target/107671] i386: Missed optimization: use of bt in bit test pattern (using -O2 -mtune=core2)

[ibuclaw at gdcproject dot org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107671

--- Comment #1 from Iain Buclaw <ibuclaw at gdcproject dot org> ---
Non-pointer variants also not detected.
---
int bt32v_setb(const __UINT32_TYPE__ v, __UINT32_TYPE__ bitnum)
{
    return ((v & (1  << (bitnum & 31)))) != 0;
}

int bt64v_setb(const __UINT64_TYPE__ v, __UINT64_TYPE__ bitnum)
{
    return ((v & (1L << (bitnum & 63)))) != 0;
}

int bt32v_setb2(const __UINT32_TYPE__ v, __UINT32_TYPE__ bitnum)
{
    return (v >> (bitnum & 31)) & 1;
}

int bt64v_setb2(const __UINT64_TYPE__ v, __UINT64_TYPE__ bitnum)
{
    return (v >> (bitnum & 63)) & 1;
}

int bt32v_setae(const __UINT32_TYPE__ v, __UINT32_TYPE__ bitnum)
{
    return ((v & (1  << (bitnum & 31)))) == 0;
}

int bt64v_setae(const __UINT64_TYPE__ v, __UINT64_TYPE__ bitnum)
{
    return ((v & (1L << (bitnum & 63)))) == 0;
}

int bt32v_setae2(const __UINT32_TYPE__ v, __UINT32_TYPE__ bitnum)
{
    return !((v >> (bitnum & 31)) & 1);
}

int bt64v_setae2(const __UINT64_TYPE__ v, __UINT64_TYPE__ bitnum)
{
    return !((v >> (bitnum & 63)) & 1);
}

[Bug target/107671] i386: Missed optimization: use of bt in bit test pattern (using -O2 -mtune=core2)

[ibuclaw at gdcproject dot org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107671

--- Comment #2 from Iain Buclaw <ibuclaw at gdcproject dot org> ---
Expected generated code would be:
---
bt32_setb*:
  ...
  shrl    $5, %edx
  movl    (%eax,%edx,4), %edx
  xorl    %eax, %eax
  btl     %ecx, %edx
  setb    %al
  ...
---
bt32_setae*:
  ...
  shrl    $5, %edx
  movl    (%eax,%edx,4), %edx
  xorl    %eax, %eax
  btl     %ecx, %edx
  setae   %al
  ...
---
bt32v_setb*:
  ...
  xorl    %eax, %eax
  btl     %esi, %edi
  setb    %al
  ...
---
bt32v_setae*:
  ...
  xorl    %eax, %eax
  btl     %esi, %edi
  setae   %al
  ...
---
bt64_setb*:
  ...
  shrq    $6, %rax
  movq    (%rdi,%rax,8), %rcx
  xorl    %eax, %eax
  btq     %rsi, %rcx 
  setb    %al
  ...
---
bt64_setae*:
  ...
  shrq    $6, %rax
  movq    (%rdi,%rax,8), %rcx
  xorl    %eax, %eax
  btq     %rsi, %rcx 
  setae   %al
  ...
---
bt64v_setb*:
  ...
  xorl    %eax, %eax
  btq     %rsi, %rdi
  setb    %al
  ...
---
bt64v_setae*:
  ...
  xorl    %eax, %eax
  btq     %rsi, %rdi
  setae   %al
  ...

[Bug target/107671] i386: Missed optimization: use of bt in bit test pattern (using -O2 -mtune=core2)

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107671

--- Comment #3 from Hongtao.liu <crazylht at gmail dot com> ---
We already have
----------cut from i386.md--------
15204;; Help combine recognize bt followed by setc
15205(define_insn_and_split "*bt<mode>_setcqi"
15206  [(set (subreg:SWI48 (match_operand:QI 0 "register_operand") 0)
15207        (zero_extract:SWI48
15208         (match_operand:SWI48 1 "register_operand")
15209         (const_int 1)
15210         (zero_extend:SI (match_operand:QI 2 "register_operand"))))
15211   (clobber (reg:CC FLAGS_REG))]
15212  "TARGET_USE_BT && ix86_pre_reload_split ()"
....

15262;; Help combine recognize bt followed by setnc
15263(define_insn_and_split "*bt<mode>_setncqi"
15264  [(set (match_operand:QI 0 "register_operand")
15265        (and:QI
15266         (not:QI
15267          (subreg:QI
15268           (lshiftrt:SWI48 (match_operand:SWI48 1 "register_operand")
15269                           (match_operand:QI 2 "register_operand")) 0))
15270         (const_int 1)))
15271   (clobber (reg:CC FLAGS_REG))]
15272  "TARGET_USE_BT && ix86_pre_reload_split ()"
15273  "#"
15274  "&& 1"


-----------cut end-------------

Guess we need more variants for that.

[Bug target/107671] i386: Missed optimization: use of bt in bit test pattern (using -O2 -mtune=core2)

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107671

--- Comment #4 from Uroš Bizjak <ubizjak at gmail dot com> ---
Created attachment 53901
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=53901&action=edit
Patch that adds relevant zero_extract patterns

This patch adds relevant zero_extract patterns that optimize:

    return ((v & (1  << (bitnum & 31)))) != 0;
    return ((v & (1L << (bitnum & 63)))) != 0;
    return (v >> (bitnum & 31)) & 1;
    return (v >> (bitnum & 63)) & 1;

from:
        movl    %esi, %ecx
        movl    $1, %eax
        sall    %cl, %eax
        testl   %edi, %eax
        setne   %al
        movzbl  %al, %eax

to:
        xorl    %eax, %eax
        btl     %esi, %edi
        setc    %al

The patch adapts *jcc_bt patterns to similar *scc_bt patterns.

Please note that the patch optimizes only to SETB conditional set instruction,
since it builds on a combine transformation to the ZERO_EXTRACT rtx.

[Bug target/107671] i386: Missed optimization: use of bt in bit test pattern (using -O2 -mtune=core2)

[ibuclaw at gdcproject dot org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107671

--- Comment #5 from Iain Buclaw <ibuclaw at gdcproject dot org> ---
(In reply to Uroš Bizjak from comment #4)
> from:
>         movl    %esi, %ecx
>         movl    $1, %eax
>         sall    %cl, %eax
>         testl   %edi, %eax
>         setne   %al
>         movzbl  %al, %eax
> 
> to:
>         xorl    %eax, %eax
>         btl     %esi, %edi
>         setc    %al
> 
> The patch adapts *jcc_bt patterns to similar *scc_bt patterns.
Thanks, have been tinkering with the pointer index version, and found that I
can coax scc_bt_mask to match if I cast the lhs to a signed type. It's not
obvious to me why there would be a difference.

    return ((__INT32_TYPE__)p[bitnum >> 5] & (1 << (bitnum & 31))) != 0;

        movl    %esi, %eax
        shrl    $5, %eax
        movl    (%rdi,%rax,4), %eax
        btl     %esi, %eax
        setc    %al


Things get even stranger once I expand to "bit test and op" variants though
(better to put in another PR though)

    __INT32_TYPE__ btc32(__UINT32_TYPE__ *p, __UINT32_TYPE__ bitnum)
    {
        __INT32_TYPE__ result = ((__INT32_TYPE__)p[bitnum >> 5]
                                     & (1 << (bitnum & 31))) != 0;
        p[bitnum >> 5] ^= 1 << (bitnum & 31);
        return result;
    }

Patch changes code-gen in the following way.

from:
        movl    %esi, %eax
        movl    %esi, %ecx
        shrl    $5, %eax
        leaq    (%rdi,%rax,4), %rdx
        movl    (%rdx), %eax
        movl    %eax, %esi
        sarl    %cl, %eax
        btcl    %ecx, %esi
        andl    $1, %eax
        movl    %esi, (%rdx)

to:
        movl    %esi, %eax
        shrl    $5, %eax
        leaq    (%rdi,%rax,4), %rdx
        movl    (%rdx), %eax
        movl    %eax, %ecx
        btcl    %esi, %ecx
        btl     %esi, %eax
        setc    %al
        movl    %ecx, (%rdx)
        movzbl  %al, %eax

[Bug target/107671] i386: Missed optimization: use of bt in bit test pattern (using -O2 -mtune=core2)

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107671

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Severity|normal                      |enhancement

[Bug target/107671] i386: Missed optimization: use of bt in bit test pattern (using -O2 -mtune=core2)

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107671

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2023-11-12
             Status|UNCONFIRMED                 |NEW

--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.

bt32_setb2, bt32v_setb, bt32v_setb2 are the only ones done for 64bit.