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From: "ibuclaw at gdcproject dot org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/107671] i386: Missed optimization: use of bt in bit test pattern (using -O2 -mtune=core2)
Date: Tue, 15 Nov 2022 16:19:02 +0000	[thread overview]
Message-ID: <bug-107671-4-WL5xA5WfkT@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-107671-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107671

--- Comment #5 from Iain Buclaw <ibuclaw at gdcproject dot org> ---
(In reply to Uroš Bizjak from comment #4)
> from:
>         movl    %esi, %ecx
>         movl    $1, %eax
>         sall    %cl, %eax
>         testl   %edi, %eax
>         setne   %al
>         movzbl  %al, %eax
> 
> to:
>         xorl    %eax, %eax
>         btl     %esi, %edi
>         setc    %al
> 
> The patch adapts *jcc_bt patterns to similar *scc_bt patterns.
Thanks, have been tinkering with the pointer index version, and found that I
can coax scc_bt_mask to match if I cast the lhs to a signed type. It's not
obvious to me why there would be a difference.

    return ((__INT32_TYPE__)p[bitnum >> 5] & (1 << (bitnum & 31))) != 0;

        movl    %esi, %eax
        shrl    $5, %eax
        movl    (%rdi,%rax,4), %eax
        btl     %esi, %eax
        setc    %al


Things get even stranger once I expand to "bit test and op" variants though
(better to put in another PR though)

    __INT32_TYPE__ btc32(__UINT32_TYPE__ *p, __UINT32_TYPE__ bitnum)
    {
        __INT32_TYPE__ result = ((__INT32_TYPE__)p[bitnum >> 5]
                                     & (1 << (bitnum & 31))) != 0;
        p[bitnum >> 5] ^= 1 << (bitnum & 31);
        return result;
    }

Patch changes code-gen in the following way.

from:
        movl    %esi, %eax
        movl    %esi, %ecx
        shrl    $5, %eax
        leaq    (%rdi,%rax,4), %rdx
        movl    (%rdx), %eax
        movl    %eax, %esi
        sarl    %cl, %eax
        btcl    %ecx, %esi
        andl    $1, %eax
        movl    %esi, (%rdx)

to:
        movl    %esi, %eax
        shrl    $5, %eax
        leaq    (%rdi,%rax,4), %rdx
        movl    (%rdx), %eax
        movl    %eax, %ecx
        btcl    %esi, %ecx
        btl     %esi, %eax
        setc    %al
        movl    %ecx, (%rdx)
        movzbl  %al, %eax

  parent reply	other threads:[~2022-11-15 16:19 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-14  3:38 [Bug target/107671] New: i386: Missed optimization: use of bt in bit test pattern when LHS is an array index ibuclaw at gdcproject dot org
2022-11-14  3:44 ` [Bug target/107671] i386: Missed optimization: use of bt in bit test pattern (using -O2 -mtune=core2) ibuclaw at gdcproject dot org
2022-11-14  4:00 ` ibuclaw at gdcproject dot org
2022-11-15  1:27 ` crazylht at gmail dot com
2022-11-15 13:15 ` ubizjak at gmail dot com
2022-11-15 16:19 ` ibuclaw at gdcproject dot org [this message]
2023-11-12 22:41 ` pinskia at gcc dot gnu.org
2023-11-12 22:46 ` pinskia at gcc dot gnu.org

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