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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/107674] [11/12/13 Regressions] arm: MVE codegen
 regressions on VCTP and vector LDR/STR instructions
Date: Thu, 06 Apr 2023 15:36:53 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D107674

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Earnshaw <rearnsha@gcc.gnu.or=
g>:

https://gcc.gnu.org/g:ddc9b5ee13cd686c8674f92d46045563c06a23ea

commit r13-7114-gddc9b5ee13cd686c8674f92d46045563c06a23ea
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Thu Apr 6 14:44:30 2023 +0100

    arm: mve: fix auto-inc generation [PR107674]

    My change r13-416-g485a0ae0982abe caused the compiler to stop
    generating auto-inc operations on mve loads and stores.  The fix
    is to check whether there is a replacement register available
    when in strict mode and the register is still a pseudo.

    gcc:

            PR target/107674
            * config/arm/arm.cc (arm_effective_regno): New function.
            (mve_vector_mem_operand): Use it.=