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From: "stammark at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/107674] New: [11/12/13 Regressions] arm: MVE codegen
 regressions on VCTP and vector LDR/STR instructions
Date: Mon, 14 Nov 2022 11:00:13 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D107674

            Bug ID: 107674
           Summary: [11/12/13 Regressions] arm: MVE codegen regressions on
                    VCTP and vector LDR/STR instructions
           Product: gcc
           Version: 12.2.1
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: stammark at gcc dot gnu.org
  Target Milestone: ---

We've found a couple of performance regressions with Arm MVE.  These can be
seen here:
https://godbolt.org/z/onPjfW4zj

* Between GCC 11 and 12 we seem to have started emitting a strange
vmrs/sxth/vmsr instruction sequence after the vctp instruction.  I suspect =
this
is something to do with the introduction of MODE_VECTOR_BOOL during that
period.

* Between GCC 12 and 13 we are no longer merging the pointer increments by =
#16=20
into the ldr/strs and we have some random movs that aren't needed either.  =
This
also happened in GCC 11, but we want to keep the improved codegen of GCC 12
here ;)

  This looks like a change in register allocation:

      Choosing alt 0 in insn 24:  (0) =3Dw  (1) Ux  (2) Up {mve_vldrhq_z_sv=
8hi}
      Creating newreg=3D149, assigning class CORE_REGS to INC/DEC result r1=
49
      Creating newreg=3D150 from oldreg=3D134, assigning class VPR_REG to r=
150
bad vs good
      Choosing alt 0 in insn 24:  (0) =3Dw  (1) Ux  (2) Up {mve_vldrhq_z_sv=
8hi}
      Creating newreg=3D149 from oldreg=3D134, assigning class VPR_REG to r=
149

Does anyone have any further ideas on why these may have changed or how to =
fix
them?

Thanks!=