[Bug rtl-optimization/107775] New: misoptimization in vec_set lower part of vector in the memory.

["crazylht at gmail dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107775

            Bug ID: 107775
           Summary: misoptimization in vec_set lower part of vector in the
                    memory.
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: crazylht at gmail dot com
                CC: tnfchris at gcc dot gnu.org
  Target Milestone: ---
            Target: aarch64-linux-gnu

The case is found when i'm looking at
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606373.html, currently
x86 gcc can optimize set_lower same as set_lower1, but not after adjusting in
can_change_mode_class. The issue can be reproduce with aarch64 gcc. I'm looking
at rtl dump, the main difference comes from subreg1, where currently it will
split 128-bit load/store into 2 64-bit load/stores which expose the opportunity
to optimize the upper 64-bit load/store off.

typedef double v2df __attribute__((vector_size(16)));

v2df reg;
void
set_lower (double b)
{
  double v[2];
  *((v2df*)&v[0]) = reg;
  v[0] = b;
  reg = *((v2df*)&v[0]);
}


void
set_lower1 (double b)
{
    reg[0] = b;
}