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From: "crazylht at gmail dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/107892] Unnecessary move between ymm registers in loop using AVX2 intrinsic Date: Mon, 28 Nov 2022 08:43:22 +0000 [thread overview] Message-ID: <bug-107892-4-Sq1ucvGS6V@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-107892-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107892 --- Comment #3 from Hongtao.liu <crazylht at gmail dot com> --- > In the bad version, I noticed that the RTL initially has two separate insns > for 'a += *p': one to do the addition and write the result to a new pseudo > register, and one to convert the value from mode V8SI to V4DI and assign it Because we're defining __m256i as __v4di, and rtl use subreg to bitcast __v8si reg to __v4di one. > to the original pseudo register. These two separate insns never get > combined. (That sort of explains why the bug isn't seen with the __v8si and > += method; gcc doesn't do a type conversion with that method.) So, I'm Combine failed to combine them because the __v8si reg is also used outside of the loop. > wondering if the bug is in the instruction combining pass. Or perhaps the > RTL should never have had two separate insns in the first place?
prev parent reply other threads:[~2022-11-28 8:43 UTC|newest] Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-28 7:41 [Bug rtl-optimization/107892] New: " ebiggers3 at gmail dot com 2022-11-28 8:15 ` [Bug rtl-optimization/107892] " ebiggers3 at gmail dot com 2022-11-28 8:23 ` ebiggers3 at gmail dot com 2022-11-28 8:43 ` crazylht at gmail dot com [this message]
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