[Bug target/108038] GCC generates poor code for select of consecutive constants on riscv-64

["rzinsly at ventanamicro dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108038

--- Comment #1 from Raphael M Zinsly <rzinsly at ventanamicro dot com> ---
(In reply to Jeffrey A. Law from comment #0)
> testGT:
>         sgt     a0,a0,a1        # 25    [c=4 l=4]  *sgt_didi
>         xori    a0,a0,1 # 27    [c=4 l=4]  xordi3/1
>         addi    a0,a0,2 # 16    [c=4 l=4]  adddi3/1
>         ret             # 35    [c=0 l=4]  simple_return
> 
> 
> But ISTM we could generate this instead:
> 
> testGT:
>         sgt     a0,a1,a0        # 24    [c=4 l=4]  *riscv.md:2535
>         addi    a0,a0,2 # 16    [c=4 l=4]  adddi3/1
>         ret             # 32    [c=0 l=4]  simple_return
Unless I'm missing something this seems wrong: 'sgt a0,a0,a1' with 'xori
a0,a0,1' would be equivalent to 'sge a0,a1,a0' or to 'sle a0,a0,a1' and not to
'sgt a0,a1,a0'.
For x == y the result would be 2 with your asm.

> We can invert the condition and swap the operands with something like this:
> 
> (define_insn ""
>   [(set (match_operand:GPR           0 "register_operand" "=r")
>     (any_le:GPR (match_operand:X 1 "register_operand" " r")
>             (match_operand:X 2 "register_operand" "r")))]
>   ""
>   "sgt<u>\t%0,%2,%1"
>   [(set_attr "type" "slt")
>    (set_attr "mode" "<X:MODE>")])
This works as you intended. However, I think the right patter should be:

(define_insn "*sge<u>_<X:mode><GPR:mode>_inv"
  [(set (match_operand:GPR 0 "register_operand" "=r")
    (any_le:GPR (match_operand:X 1 "register_operand" " r")
            (match_operand:X 2 "register_operand" "r")))]
  ""
  "sge<u>\t%0,%2,%1"
  [(set_attr "type" "slt")
   (set_attr "mode" "<X:MODE>")])

It produces the output:

testGT:
        sge     a0,a1,a0        # 24    [c=4 l=4]  *sge_didi_inv
        addi    a0,a0,2 # 16    [c=4 l=4]  adddi3/1
        ret             # 32    [c=0 l=4]  simple_return