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From: "jiawei at iscas dot ac.cn" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/108185] [RISC-V]RVV assemble not set vsetvli correct.
Date: Tue, 20 Dec 2022 03:58:27 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108185

jiawei <jiawei at iscas dot ac.cn> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Version|13.0                        |fortran-dev

--- Comment #1 from jiawei <jiawei at iscas dot ac.cn> ---
        vl1re8.v        v25,0(a0)
        sub     a5,a3,a5
        vs1r.v  v25,0(a1)
        vs1r.v  v25,0(a5)
        addi    a4,a1,800
        csrr    t0,vlenb
        slli    t1,t0,1
        vsetvli a5,zero,e8,m1,ta,ma
        vsm.v   v25,0(a4)=