From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id BE7AF3858D3C; Wed, 28 Dec 2022 19:07:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BE7AF3858D3C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1672254472; bh=C3fbOc+TL+OrOB7MnK+H/j15p2iPYI0834CaqB5QjgY=; h=From:To:Subject:Date:From; b=SVEIKp15QDRYq1aSKfyxFpaLA3AyUH/cT71uSnkasJSoAd/VhulU9u4Xg8tvKhpzH +2VvXTeRy0h3LMzFXLeMdbgj4oRk7OEF/kn8c8+fBhxO0PBxecn8PRtwmO5Gd/dRAY 9SYKKmW4j0YDXiOFeQFvxEoASoBY6rDZmAFHg3fI= From: "law at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/108247] New: Missed opportunity to generate shNadd on risc-v Date: Wed, 28 Dec 2022 19:07:52 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: law at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter cc target_milestone cf_gcctarget Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108247 Bug ID: 108247 Summary: Missed opportunity to generate shNadd on risc-v Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org CC: rzinsly at ventanamicro dot com Target Milestone: --- Target: risc-v int sub2(int a, long long b) { b =3D (b << 32) >> 31; unsigned int x =3D a + b; return x; } When compiled with Zba should ideally generate something like this: sh1add a0, a1, a0 sext.w a0, a0 ret I suspect we need to match something like this as a define_split: Failed to match this instruction: (set (reg:SI 142 [ x ]) (plus:SI (subreg:SI (and:DI (ashift:DI (reg:DI 146) (const_int 1 [0x1])) (const_int 4294967294 [0xfffffffe])) 0) (subreg:SI (reg:DI 145) 0))) Or this: (set (reg:DI 144 [ x ]) (sign_extend:DI (plus:SI (subreg:SI (and:DI (ashift:DI (reg:DI 146) (const_int 1 [0x1])) (const_int 4294967294 [0xfffffffe])) 0) (subreg:SI (reg:DI 145) 0))))=