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From: "acoplan at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug tree-optimization/108430] New: [13 Regression] Wrong code with
 -msve-vector-bits=512 since r13-707-g68e0063397
Date: Tue, 17 Jan 2023 11:10:52 +0000
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X-Bugzilla-Component: tree-optimization
X-Bugzilla-Version: 13.0
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108430

            Bug ID: 108430
           Summary: [13 Regression] Wrong code with -msve-vector-bits=3D512
                    since r13-707-g68e0063397
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: tree-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: acoplan at gcc dot gnu.org
  Target Milestone: ---

For the following testcase:

static long d;
static int i =3D 37;
static unsigned long a[22];
static unsigned short c[22];
static unsigned g[80];
static unsigned short *h =3D c;
static unsigned long *j =3D a;
int main() {
  for (long m =3D 0; m < 8; ++m)
    d =3D 1;
  for (unsigned char p =3D 0; p < 17; p +=3D (d ? i : 0) - 35)
  {
    long t =3D h[p] ? i : j[p];
    g[p] =3D t;
  }
  if (g[0])
    __builtin_abort ();
}

we appear to miscompile it with -O3 -march=3Darmv8.2-a+sve -msve-vector-bit=
s=3D512
since r13-707-g68e0063397ba820e71adc220b2da0581dce29ffa :


commit 68e0063397ba820e71adc220b2da0581dce29ffa (HEAD, refs/bisect/bad)=20=
=20=20=20=20=20=20=20=20
Author: Richard Biener <rguenther@suse.de>=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20
Date:   Mon Apr 11 12:36:53 2022=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20

    Force the selection operand of a GIMPLE COND_EXPR to be a register=