From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-bugzilla@gcc.gnu.org>
Received: by sourceware.org (Postfix, from userid 48)
	id 7AB7C3881D08; Mon, 13 Feb 2023 19:24:14 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7AB7C3881D08
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;
	s=default; t=1676316254;
	bh=4cU+uhDqBB1PNLkVmH5HVRd+ldHMBgtoW5n6lVl6KYE=;
	h=From:To:Subject:Date:In-Reply-To:References:From;
	b=CTaCKSsY8q72NWY2ZgwC1XJAEd9aUMpu9eUGeW0X22FwoavJjtfDTwXQahoYsdp5u
	 OnMrLjXVik5N+4e4B8SMZIAwQFbGAuTmZyzFABXmuBDE+kCK2B47+zCDS0E9VkFuQF
	 EjP/jD/nFl+RbUrhN+gK4c23HOWHm3gnceYHDmX4=
From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/108516] Useless movzx instruction emitted when loading 8
 bits from 24 bit struct
Date: Mon, 13 Feb 2023 19:24:13 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: target
X-Bugzilla-Version: 12.2.0
X-Bugzilla-Keywords: missed-optimization
X-Bugzilla-Severity: enhancement
X-Bugzilla-Who: cvs-commit at gcc dot gnu.org
X-Bugzilla-Status: ASSIGNED
X-Bugzilla-Resolution: 
X-Bugzilla-Priority: P3
X-Bugzilla-Assigned-To: ubizjak at gmail dot com
X-Bugzilla-Target-Milestone: ---
X-Bugzilla-Flags: 
X-Bugzilla-Changed-Fields: 
Message-ID: <bug-108516-4-hRgQerifWF@http.gcc.gnu.org/bugzilla/>
In-Reply-To: <bug-108516-4@http.gcc.gnu.org/bugzilla/>
References: <bug-108516-4@http.gcc.gnu.org/bugzilla/>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/
Auto-Submitted: auto-generated
MIME-Version: 1.0
List-Id: <gcc-bugs.sourceware.org>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108516

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:00b8a212ea2132fb68e42488317392346e169035

commit r13-5969-g00b8a212ea2132fb68e42488317392346e169035
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Mon Feb 13 17:17:46 2023 +0100

    i386: Relax extract location operand mode requirements [PR108516]

    Combine pass simplifies zero-extend of a zero-extract to:

    Trying 16 -> 6:
       16: r86:QI#0=3Dzero_extract(r87:HI,0x8,0x8)
          REG_DEAD r87:HI
        6: r84:SI=3Dzero_extend(r86:QI)
          REG_DEAD r86:QI
    Failed to match this instruction:
    (set (reg:SI 84 [ s.e2 ])
        (zero_extract:SI (reg:HI 87)
            (const_int 8 [0x8])
            (const_int 8 [0x8])))

    which fails instruction recognision.  The pattern is valid, since there
    is no requirement on the mode of the location operand.

    The patch relaxes location operand mode requirements of *extzv and *extv
    insn patterns to allow all supported integer modes.  The patch also
    adds support for a related sign-extend from zero-extracted operand.

    2023-02-13  Uro=C3=85=C2=A1 Bizjak  <ubizjak@gmail.com>

    gcc/ChangeLog:

            PR target/108516
            * config/i386/predicates.md (extr_register_operand):
            New special predicate.
            * config/i386/i386.md (*extv<mode>): Use extr_register_operand
            as operand 1 predicate.
            (*exzv<mode>): Ditto.
            (*extendqi<SWI24:mode>_ext_1): New insn pattern.

    gcc/testsuite/ChangeLog:

            PR target/108516
            * gcc.target/i386/pr108516-1.c: New test.
            * gcc.target/i386/pr108516-2.c: Ditto.=