* [Bug target/108516] Useless movzx instruction emitted when loading 8 bits from 24 bit struct
2023-01-24 11:01 [Bug rtl-optimization/108516] New: Useless movzx instruction emitted when loading 8 bits from 24 bit struct jzwinck at gmail dot com
@ 2023-01-24 13:15 ` pinskia at gcc dot gnu.org
2023-01-24 13:15 ` pinskia at gcc dot gnu.org
` (7 subsequent siblings)
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From: pinskia at gcc dot gnu.org @ 2023-01-24 13:15 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108516
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2023-01-24
Ever confirmed|0 |1
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed:
Trying 16 -> 6:
16: r86:QI#0=zero_extract(r87:HI,0x8,0x8)
REG_DEAD r87:HI
6: r84:SI=zero_extend(r86:QI)
REG_DEAD r86:QI
Failed to match this instruction:
(set (reg:SI 84 [ s.e2 ])
(zero_extract:SI (reg:HI 87)
(const_int 8 [0x8])
(const_int 8 [0x8])))
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Bug target/108516] Useless movzx instruction emitted when loading 8 bits from 24 bit struct
2023-01-24 11:01 [Bug rtl-optimization/108516] New: Useless movzx instruction emitted when loading 8 bits from 24 bit struct jzwinck at gmail dot com
2023-01-24 13:15 ` [Bug target/108516] " pinskia at gcc dot gnu.org
@ 2023-01-24 13:15 ` pinskia at gcc dot gnu.org
2023-01-24 13:18 ` [Bug rtl-optimization/108516] " pinskia at gcc dot gnu.org
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: pinskia at gcc dot gnu.org @ 2023-01-24 13:15 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108516
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Severity|normal |enhancement
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Bug rtl-optimization/108516] Useless movzx instruction emitted when loading 8 bits from 24 bit struct
2023-01-24 11:01 [Bug rtl-optimization/108516] New: Useless movzx instruction emitted when loading 8 bits from 24 bit struct jzwinck at gmail dot com
2023-01-24 13:15 ` [Bug target/108516] " pinskia at gcc dot gnu.org
2023-01-24 13:15 ` pinskia at gcc dot gnu.org
@ 2023-01-24 13:18 ` pinskia at gcc dot gnu.org
2023-01-28 7:36 ` crazylht at gmail dot com
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: pinskia at gcc dot gnu.org @ 2023-01-24 13:18 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108516
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Component|target |rtl-optimization
--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Andrew Pinski from comment #1)
> Confirmed:
>
> Trying 16 -> 6:
> 16: r86:QI#0=zero_extract(r87:HI,0x8,0x8)
> REG_DEAD r87:HI
> 6: r84:SI=zero_extend(r86:QI)
> REG_DEAD r86:QI
> Failed to match this instruction:
> (set (reg:SI 84 [ s.e2 ])
> (zero_extract:SI (reg:HI 87)
> (const_int 8 [0x8])
> (const_int 8 [0x8])))
Hmm, is this even valid RTL that combine is producing ...
If there was a subreg to SI mode there from the HI mode reg, it would match
correctly.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Bug rtl-optimization/108516] Useless movzx instruction emitted when loading 8 bits from 24 bit struct
2023-01-24 11:01 [Bug rtl-optimization/108516] New: Useless movzx instruction emitted when loading 8 bits from 24 bit struct jzwinck at gmail dot com
` (2 preceding siblings ...)
2023-01-24 13:18 ` [Bug rtl-optimization/108516] " pinskia at gcc dot gnu.org
@ 2023-01-28 7:36 ` crazylht at gmail dot com
2023-02-10 22:07 ` pinskia at gcc dot gnu.org
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: crazylht at gmail dot com @ 2023-01-28 7:36 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108516
Hongtao.liu <crazylht at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |crazylht at gmail dot com
--- Comment #3 from Hongtao.liu <crazylht at gmail dot com> ---
> Hmm, is this even valid RTL that combine is producing ...
If it's valid for different modes between zero_extract and mode of {loc}, we
can directly add an insn to match that.
The documents doesn't mention any requirement for mode {m} and {loc}
2892@findex zero_extract
2893@item (zero_extract:@var{m} @var{loc} @var{size} @var{pos})
2894Like @code{sign_extract} but refers to an unsigned or zero-extended
2895bit-field. The same sequence of bits are extracted, but they
2896are filled to an entire word with zeros instead of by sign-extension.
2897
2898Unlike @code{sign_extract}, this type of expressions can be lvalues
2899in RTL; they may appear on the left side of an assignment, indicating
2900insertion of a value into the specified bit-field.
2901@end table
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Bug rtl-optimization/108516] Useless movzx instruction emitted when loading 8 bits from 24 bit struct
2023-01-24 11:01 [Bug rtl-optimization/108516] New: Useless movzx instruction emitted when loading 8 bits from 24 bit struct jzwinck at gmail dot com
` (3 preceding siblings ...)
2023-01-28 7:36 ` crazylht at gmail dot com
@ 2023-02-10 22:07 ` pinskia at gcc dot gnu.org
2023-02-10 22:34 ` levo.delellis at gmail dot com
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: pinskia at gcc dot gnu.org @ 2023-02-10 22:07 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108516
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |levo.delellis at gmail dot com
--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
*** Bug 108756 has been marked as a duplicate of this bug. ***
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Bug rtl-optimization/108516] Useless movzx instruction emitted when loading 8 bits from 24 bit struct
2023-01-24 11:01 [Bug rtl-optimization/108516] New: Useless movzx instruction emitted when loading 8 bits from 24 bit struct jzwinck at gmail dot com
` (4 preceding siblings ...)
2023-02-10 22:07 ` pinskia at gcc dot gnu.org
@ 2023-02-10 22:34 ` levo.delellis at gmail dot com
2023-02-13 8:49 ` ubizjak at gmail dot com
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: levo.delellis at gmail dot com @ 2023-02-10 22:34 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108516
--- Comment #5 from Levo DeLellis <levo.delellis at gmail dot com> ---
Here's a testcase for the same problem
struct T2 { bool a, b; };
static T2 test();
int myfunc() {
auto [a, b] = test();
return ((int)a<<1) + b;
}
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Bug rtl-optimization/108516] Useless movzx instruction emitted when loading 8 bits from 24 bit struct
2023-01-24 11:01 [Bug rtl-optimization/108516] New: Useless movzx instruction emitted when loading 8 bits from 24 bit struct jzwinck at gmail dot com
` (5 preceding siblings ...)
2023-02-10 22:34 ` levo.delellis at gmail dot com
@ 2023-02-13 8:49 ` ubizjak at gmail dot com
2023-02-13 19:24 ` [Bug target/108516] " cvs-commit at gcc dot gnu.org
2023-02-13 20:04 ` [Bug target/108516] [11/12 Regression] " ubizjak at gmail dot com
8 siblings, 0 replies; 10+ messages in thread
From: ubizjak at gmail dot com @ 2023-02-13 8:49 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108516
Uroš Bizjak <ubizjak at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |ASSIGNED
Assignee|unassigned at gcc dot gnu.org |ubizjak at gmail dot com
--- Comment #6 from Uroš Bizjak <ubizjak at gmail dot com> ---
Created attachment 54454
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54454&action=edit
patch to relax extract modes
This patch relaxes extract and insert operand modes to no longer match op mode.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Bug target/108516] Useless movzx instruction emitted when loading 8 bits from 24 bit struct
2023-01-24 11:01 [Bug rtl-optimization/108516] New: Useless movzx instruction emitted when loading 8 bits from 24 bit struct jzwinck at gmail dot com
` (6 preceding siblings ...)
2023-02-13 8:49 ` ubizjak at gmail dot com
@ 2023-02-13 19:24 ` cvs-commit at gcc dot gnu.org
2023-02-13 20:04 ` [Bug target/108516] [11/12 Regression] " ubizjak at gmail dot com
8 siblings, 0 replies; 10+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2023-02-13 19:24 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108516
--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:
https://gcc.gnu.org/g:00b8a212ea2132fb68e42488317392346e169035
commit r13-5969-g00b8a212ea2132fb68e42488317392346e169035
Author: Uros Bizjak <ubizjak@gmail.com>
Date: Mon Feb 13 17:17:46 2023 +0100
i386: Relax extract location operand mode requirements [PR108516]
Combine pass simplifies zero-extend of a zero-extract to:
Trying 16 -> 6:
16: r86:QI#0=zero_extract(r87:HI,0x8,0x8)
REG_DEAD r87:HI
6: r84:SI=zero_extend(r86:QI)
REG_DEAD r86:QI
Failed to match this instruction:
(set (reg:SI 84 [ s.e2 ])
(zero_extract:SI (reg:HI 87)
(const_int 8 [0x8])
(const_int 8 [0x8])))
which fails instruction recognision. The pattern is valid, since there
is no requirement on the mode of the location operand.
The patch relaxes location operand mode requirements of *extzv and *extv
insn patterns to allow all supported integer modes. The patch also
adds support for a related sign-extend from zero-extracted operand.
2023-02-13 Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/108516
* config/i386/predicates.md (extr_register_operand):
New special predicate.
* config/i386/i386.md (*extv<mode>): Use extr_register_operand
as operand 1 predicate.
(*exzv<mode>): Ditto.
(*extendqi<SWI24:mode>_ext_1): New insn pattern.
gcc/testsuite/ChangeLog:
PR target/108516
* gcc.target/i386/pr108516-1.c: New test.
* gcc.target/i386/pr108516-2.c: Ditto.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Bug target/108516] [11/12 Regression] Useless movzx instruction emitted when loading 8 bits from 24 bit struct
2023-01-24 11:01 [Bug rtl-optimization/108516] New: Useless movzx instruction emitted when loading 8 bits from 24 bit struct jzwinck at gmail dot com
` (7 preceding siblings ...)
2023-02-13 19:24 ` [Bug target/108516] " cvs-commit at gcc dot gnu.org
@ 2023-02-13 20:04 ` ubizjak at gmail dot com
8 siblings, 0 replies; 10+ messages in thread
From: ubizjak at gmail dot com @ 2023-02-13 20:04 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108516
Uroš Bizjak <ubizjak at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Summary|Useless movzx instruction |[11/12 Regression] Useless
|emitted when loading 8 bits |movzx instruction emitted
|from 24 bit struct |when loading 8 bits from 24
| |bit struct
Severity|enhancement |normal
Known to fail| |12.2.0
Status|ASSIGNED |RESOLVED
Target Milestone|--- |13.0
--- Comment #8 from Uroš Bizjak <ubizjak at gmail dot com> ---
Fixed.
^ permalink raw reply [flat|nested] 10+ messages in thread