From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 7999E3858C83; Mon, 30 Jan 2023 08:06:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7999E3858C83 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1675065991; bh=dEAfp917pIPss30H5OsBSGJWNGOFm2Qqg0g0Aq236Pc=; h=From:To:Subject:Date:In-Reply-To:References:From; b=t/Xu5YsdDIiCBg9iMdbFPKRpmqBVeerzs0+U1UrFy8Pv/WuoMNX3oOwPjGthkVelu tHeDXiBhIoyMomaSyg5rhI6qf9dgR/L5NWEwA249uq0jhQwNA5fgMEXRhNb1xUIyQy FUE2On3rawQIO1n3XZWr0NnB1u6ULqutE5F7VwZ0= From: "torvalds@linux-foundation.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/108552] Linux i386 kernel 5.14 memory corruption for pre_compound_page() when gcov is enabled Date: Mon, 30 Jan 2023 08:06:29 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 11.3.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: torvalds@linux-foundation.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108552 --- Comment #43 from Linus Torvalds --- (In reply to Richard Biener from comment #42) >=20 > I think if we want to avoid doing optimizations on gcov counters we should > make them volatile.=20 Honestly, that sounds like the cleanest and safest option to me. That said, with the gcov counters apparently also being 64-bit, I suspect it will create some truly horrid code generation. Presumably you'd end up getting a lot of load-load-add-adc-store-store instruction patterns, which is not just six instructions when just two shou= ld do - it also uses up two registers. So while it sounds like the simplest and safest model, maybe it just makes = code generation too unbearably bad? Maybe nobody who uses gcov would care. But I suspect it might be quite the = big performance regression, to the point where even people who thought they don= 't care will go "that's a bit much". I wonder if there is some half-way solution that would allow at least a load-add-store-load-adc-store instruction sequence, which would then mean (= a) one less register wasted and (b) potentially allow some peephole optimizati= on turning it into just a addmem-adcmem instruction pair. Turning just the one of the memops into a volatile access might be enough (= eg just the load, but not the store?)=