From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 387563858D39; Tue, 31 Jan 2023 15:01:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 387563858D39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1675177302; bh=0EDiwwtRAouZUbyIPTBQlANSr+8BZV9op1sNCxdpqMg=; h=From:To:Subject:Date:In-Reply-To:References:From; b=a6F/kE8J1f5hFV4LMc8yd0TqkMc6zJ6FSPVc8pHCOvEjibqOSkNEL4mlpWJvurEv/ fcBSruyvfwAHnlLbG06sIj5vuk4Xq36KOkBU0meFAwywDrDEJy+3C3v5576BaGONNB GM8dXXiwTxSV6cTf6UZRlVtpWg83DrdKanUDQc9s= From: "tnfchris at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/108583] [13 Regression] wrong code with vector division by uint16 at -O2 Date: Tue, 31 Jan 2023 15:01:41 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: tnfchris at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P1 X-Bugzilla-Assigned-To: tnfchris at gcc dot gnu.org X-Bugzilla-Target-Milestone: 13.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108583 --- Comment #18 from Tamar Christina --- > >=20 > > Ack, that also tracks with what I tried before, we don't indeed track r= anges > > for vector ops. The general case can still be handled slightly better (= I think) > > but it doesn't become as clear of a win as this one. > >=20 > > > You probably did so elsewhere some time ago, but what exactly are tho= se > > > four instructions? (pointers to specifications appreciated) > >=20 > > For NEON we use: > > https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instruc= tions/ADDHN--ADDHN2--Add-returning-High-Narrow- >=20 > so thats a add + pack high >=20 Yes, though with no overflow, the addition is done in twice the precision of the original type. So it's more a widening add + pack high which narrows it back and zero extends. > > https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instruc= tions/UADDW--UADDW2--Unsigned-Add-Wide- >=20 > and that unpacks (zero-extends) the high/low part of one operand of an add >=20 > I wonder if we'd open-code the pack / unpack and use regular add whether > combine can synthesize uaddw and addhn? The pack and unpack would be > vec_perms on GIMPLE (plus V_C_E). I don't think so for addhn, because it wouldn't truncate the top bits, it truncates the bottom bits. The instruction does element1 =3D Elem[operand1, e, 2*esize]; element2 =3D Elem[operand2, e, 2*esize]; So it widens on input.=20 >=20 > So the difficulty here will be to decide whether that's in the end > better than what the pattern handling code does now, right? Because > I think most targets will be able to do the above but lacking the > special adds it will be slower because of the extra packing/unpacking? >=20 > That said, can we possibly do just that costing (would be a first in > the pattern code I guess) with a target hook? Or add optabs for > the addh operations so we can query support? We could, the alternative wouldn't be correct for costing I think.. if we generate *+ , vec_perm that's gonna be more expensive.=