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From: "rguenther at suse dot de" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/108583] [13 Regression] wrong code with vector division
 by uint16 at -O2
Date: Thu, 02 Feb 2023 08:50:04 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108583

--- Comment #22 from rguenther at suse dot de <rguenther at suse dot de> ---
On Thu, 2 Feb 2023, tnfchris at gcc dot gnu.org wrote:

> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108583
>=20
> --- Comment #21 from Tamar Christina <tnfchris at gcc dot gnu.org> ---
> >=20
> > OK, so that's an ADD_HIGHPART_EXPR then?  Though the highpart of an
> > add is only a single bit, isn't it?  For scalar you'd use the
> > carry bit here and instructions like adc to consume it.  Is addhn
> > to do such thing on vectors?
> >=20
>=20
> So I think this is the only new IFN we'd need. basically we only need one
> representing (a + b) >> n, for certain values of n we have a single instr=
uction
> for others we reject it.

But the ISA only implements n =3D=3D width(a), so a true "highpart add".
So I'd add

OPTAB_D (sadd_highpart_optab, "sadd$a3_highpart")
OPTAB_D (uadd_highpart_optab, "uadd$a3_highpart")

only?  That is it's QImode + QImode -> QImode with the carry bit in
the result (sign or zero-extended)?=