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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/108640] ICE compiling busybox for m68k in
 change_address_1, at emit-rtl.cc:2283
Date: Fri, 19 Jan 2024 23:05:59 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108640

--- Comment #8 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:a834414794d80f21550dd0591e260fc833f49eb9

commit r14-8298-ga834414794d80f21550dd0591e260fc833f49eb9
Author: Mikael Pettersson <mikpelinux@gmail.com>
Date:   Fri Jan 19 16:05:34 2024 -0700

    [PATCH] Avoid ICE in single-bit logical RMWs on m68k-uclinux [PR108640]

    When generating RMW logical operations on m68k, the backend
    recognizes single-bit operations and rewrites them as bit
    instructions on operands adjusted to address the intended byte.
    When offsetting the addresses the backend keeps the modes as
    SImode, even though the actual access will be in QImode.

    The uclinux target defines M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
    which adds a check that the adjusted operand is within the bounds
    of the original object.  Since the address has been offset it is
    not, and the compiler ICEs.

    The bug is that the modes of the adjusted operands should have been
    narrowed to QImode, which is that this patch does.  Nearby code
    which narrows to HImode gets that right.

    Bootstrapped and regression tested on m68k-linux-gnu.

    Ok for master? (Note: I don't have commit rights.)

    gcc/

            PR target/108640
            * config/m68k/m68k.cc (output_andsi3): Use QImode for
            address adjusted for 1-byte RMW access.
            (output_iorsi3): Likewise.
            (output_xorsi3): Likewise.

    gcc/testsuite/

            PR target/108640
            * gcc.target/m68k/pr108640.c: New test.=