From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 83B5D3853D0E; Mon, 3 Apr 2023 08:58:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 83B5D3853D0E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1680512285; bh=bdNaTxPGGFkiW7ovCkdrO/rzC8xh+Nv88w9tcBUm4GA=; h=From:To:Subject:Date:In-Reply-To:References:From; b=ALllCpOxUVz17eQtsMqrNPJuQPuwxVgsNch1G9GrIQpqwQQ0Fm66CW/aziFAfaeBw XRmVzbWkptBD2b3TSqbdkyfNGRQ1mOF7Xpv6SI0+xVlB/w3szdPqGwVzmgsVyd1pad Kuw9pcfTLA4rPn7B7ikcT9NJFtoN5qoCHSDBMvSg= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/108681] [12 Regression] gcc hangs compiling opencv/channels_combine.cpp for aarch64 Date: Mon, 03 Apr 2023 08:58:05 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: compile-time-hog, needs-bisection X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: REOPENED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: rsandifo at gcc dot gnu.org X-Bugzilla-Target-Milestone: 13.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108681 --- Comment #15 from CVS Commits --- The releases/gcc-12 branch has been updated by Richard Sandiford : https://gcc.gnu.org/g:61bdd3c38039e1e309d5cf78c16c4052f6e09bea commit r12-9382-g61bdd3c38039e1e309d5cf78c16c4052f6e09bea Author: Richard Sandiford Date: Mon Apr 3 09:57:08 2023 +0100 lra: Replace subregs in bare uses & clobbers [PR108681] In this PR we had a write to one vector of a 4-vector tuple. The vector had mode V1DI, and the target doesn't provide V1DI moves, so this was converted into: (clobber (subreg:V1DI (reg/v:V4x1DI 92 [ b ]) 24)) followed by a DImode move. (The clobber isn't really necessary or helpful for a single word, but would be for wider moves.) The subreg in the clobber survived until after RA: (clobber (subreg:V1DI (reg/v:V4x1DI 34 v2 [orig:92 b ] [92]) 24)) IMO this isn't well-formed. If a subreg of a hard register simplifies to a hard register, it should be replaced by the hard register. If the subreg doesn't simplify, then target-independent code can't be sure which parts of the register are affected and which aren't. A clobber of such a subreg isn't useful and (again IMO) should just be removed. Conversely, a use of such a subreg is effectively a use of the whole inner register. LRA has code to simplify subregs of hard registers, but it didn't handle bare uses and clobbers. The patch extends it to do that. One question was whether the final_p argument to alter_subregs should be true or false. True is IMO dangerous, since it forces replacements that might not be valid from a dataflow perspective, and uses and clobbers only exist for dataflow. As said above, I think the correct way of handling a failed simplification would be to delete clobbers and replace uses of subregs with uses of the inner register. But I didn't want to write untested code to do that. In the PR, the clobber caused an infinite loop in DCE, because of a disagreement about what effect the clobber had. But for the reasons above, I think that was GIGO rather than a bug in DF or DCE. gcc/ PR rtl-optimization/108681 * lra-spills.cc (lra_final_code_change): Extend subreg replacem= ent code to handle bare uses and clobbers. gcc/testsuite/ PR rtl-optimization/108681 * gcc.target/aarch64/pr108681.c: New test. (cherry picked from commit 3cac06d84f334705ed0bce12fbc3a4cec4a8fd3b)=