From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 45ED83858D32; Sun, 12 Feb 2023 11:00:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 45ED83858D32 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1676199639; bh=k/GY+xFMlIyMT6se7f6D87rvsZNp6iN+TD6N/VurGqs=; h=From:To:Subject:Date:In-Reply-To:References:From; b=IVdk4Qq8XeFYcBstHBG8kP0vcI4P+oEGzchjMLLWOf+k96Nj4VTtBfLR+20ZUbpPx +YLV4FpupVobPSIVGYK9+OTZLk9QP8dZ1T5WplHC1rGP41UHBPBX9uROnNALa4OpEZ VYiKrnZ8pI9mHbT0S8DU5ZlUI7UGnfKVkeataPcI= From: "sinan.lin at linux dot alibaba.com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/108764] [RISCV] Cost model for RVB is too aggressive Date: Sun, 12 Feb 2023 11:00:38 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: sinan.lin at linux dot alibaba.com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108764 --- Comment #5 from Sinan --- (In reply to Kito Cheng from comment #3) > > I think one solution is to change the cost model of such complex instru= ctions to the sum of the cost for each part. E.g.=20 > > cost for shNadd =3D COSTS_N_INSNS (SINGLE_SHIFT_COST) + COSTS_N_INSNS (= 1) # cost of addition >=20 > Some RISC-V core implementation did has one cycle for shNadd operation as= I > know, but I know it's not true for every implementation. Thanks for the info. Interestingly, the shNadd-like instructions(add reg1, reg2, reg3, lsl #N) in AArch64/neoverse-n1 are also one cycle operations(https://developer.arm.com/documentation/pjdoc466751330-9707/late= st), but the cost model for them is different from the one in riscv backend(AArc= h64 doesn't generate add r1, r2, r3, lsl #3 for the given test case). > Anyway, it's really uarch dependent, so I would prefer keep as it for now, > and then extend the cost model function to easier handle different uarch > (-mtune) when GCC 14 is open. Agree.=