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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/108779] AARCH64 should add an option to change TLS register location to support EL1/EL2/EL3 system registers Date: Tue, 13 Jun 2023 09:17:08 +0000 [thread overview] Message-ID: <bug-108779-4-1gW8a7l3zs@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-108779-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108779 --- Comment #11 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>: https://gcc.gnu.org/g:4389a2d2d0cc639cbeeb8453dc20bf315316d4e3 commit r14-1781-g4389a2d2d0cc639cbeeb8453dc20bf315316d4e3 Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com> Date: Tue Jun 13 10:13:55 2023 +0100 aarch64: Extend -mtp= arguments After discussing the -mtp= option with Arm's LLVM developers we'd like to extend the functionality of the option somewhat. First of all, there is another TPIDR register that can be used to read the thread pointer: TPIDRRO_EL0 (which can also be accessed by AArch32 under another name) so it makes sense to add -mtp=tpidrr0_el0. This makes the existing arguments el0, el1, el2, el3 somewhat inconsistent in their naming so this patch introduces the more "full" names tpidr_el0, tpidr_el1, tpidr_el2, tpidr_el3 and makes the above short names alias of these new ones. Long story short, we preserve backwards compatibility and add a new TPIDR register to access through -mtp that wasn't available previously. There is more relevant discussion of the options at https://reviews.llvm.org/D152433 if you're interested. Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: PR target/108779 * config/aarch64/aarch64-opts.h (enum aarch64_tp_reg): Add AARCH64_TPIDRRO_EL0 value. * config/aarch64/aarch64.cc (aarch64_output_load_tp): Define. * config/aarch64/aarch64.opt (tpidr_el0, tpidr_el1, tpidr_el2, tpidr_el3, tpidrro_el3): New accepted values to -mtp=. * doc/invoke.texi (AArch64 Options): Document new -mtp= options. gcc/testsuite/ChangeLog: PR target/108779 * gcc.target/aarch64/mtp_5.c: New test. * gcc.target/aarch64/mtp_6.c: New test. * gcc.target/aarch64/mtp_7.c: New test. * gcc.target/aarch64/mtp_8.c: New test. * gcc.target/aarch64/mtp_9.c: New test.
prev parent reply other threads:[~2023-06-13 9:17 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-13 19:56 [Bug target/108779] New: No option to change thread-pointer location on AArch64 zach-gcc at cs dot stanford.edu 2023-02-13 20:00 ` [Bug target/108779] AARCH64 should add an option to change TLS register location to support EL1/EL2/EL3 system registers pinskia at gcc dot gnu.org 2023-02-14 9:45 ` ktkachov at gcc dot gnu.org 2023-02-14 13:07 ` ktkachov at gcc dot gnu.org 2023-02-14 20:05 ` pinskia at gcc dot gnu.org 2023-02-14 21:11 ` zach-gcc at cs dot stanford.edu 2023-02-26 23:53 ` zach-gcc at cs dot stanford.edu 2023-02-26 23:55 ` pinskia at gcc dot gnu.org 2023-02-27 0:17 ` zach-gcc at cs dot stanford.edu 2023-04-21 18:00 ` cvs-commit at gcc dot gnu.org 2023-04-21 18:01 ` ktkachov at gcc dot gnu.org 2023-06-13 9:17 ` cvs-commit at gcc dot gnu.org [this message]
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