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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/108779] AARCH64 should add an option to change TLS register location to support EL1/EL2/EL3 system registers
Date: Fri, 21 Apr 2023 18:00:57 +0000 [thread overview]
Message-ID: <bug-108779-4-KfPGT0VcQa@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-108779-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108779
--- Comment #9 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:
https://gcc.gnu.org/g:573624ec90c80d1a024ab405e2575785b869a833
commit r14-154-g573624ec90c80d1a024ab405e2575785b869a833
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Fri Apr 21 19:00:02 2023 +0100
PR target/108779 aarch64: Implement -mtp= option
A user has requested that we support the -mtp= option in aarch64 GCC for
changing
the TPIDR register to read for TLS accesses. I'm not a big fan of the
option name,
but we already support it in the arm port and Clang supports it for AArch64
already,
where it accepts the 'el0', 'el1', 'el2', 'el3' values.
This patch implements the same functionality in GCC.
Bootstrapped and tested on aarch64-none-linux-gnu.
Confirmed with godbolt that the sequences and options are the same as what
Clang accepts/generates.
gcc/ChangeLog:
PR target/108779
* config/aarch64/aarch64-opts.h (enum aarch64_tp_reg): Define.
* config/aarch64/aarch64-protos.h (aarch64_output_load_tp):
Define prototype.
* config/aarch64/aarch64.cc (aarch64_tpidr_register): Declare.
(aarch64_override_options_internal): Handle the above.
(aarch64_output_load_tp): New function.
* config/aarch64/aarch64.md (aarch64_load_tp_hard): Call
aarch64_output_load_tp.
* config/aarch64/aarch64.opt (aarch64_tp_reg): Define enum.
(mtp=): New option.
* doc/invoke.texi (AArch64 Options): Document -mtp=.
gcc/testsuite/ChangeLog:
PR target/108779
* gcc.target/aarch64/mtp.c: New test.
* gcc.target/aarch64/mtp_1.c: New test.
* gcc.target/aarch64/mtp_2.c: New test.
* gcc.target/aarch64/mtp_3.c: New test.
* gcc.target/aarch64/mtp_4.c: New test.
next prev parent reply other threads:[~2023-04-21 18:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-13 19:56 [Bug target/108779] New: No option to change thread-pointer location on AArch64 zach-gcc at cs dot stanford.edu
2023-02-13 20:00 ` [Bug target/108779] AARCH64 should add an option to change TLS register location to support EL1/EL2/EL3 system registers pinskia at gcc dot gnu.org
2023-02-14 9:45 ` ktkachov at gcc dot gnu.org
2023-02-14 13:07 ` ktkachov at gcc dot gnu.org
2023-02-14 20:05 ` pinskia at gcc dot gnu.org
2023-02-14 21:11 ` zach-gcc at cs dot stanford.edu
2023-02-26 23:53 ` zach-gcc at cs dot stanford.edu
2023-02-26 23:55 ` pinskia at gcc dot gnu.org
2023-02-27 0:17 ` zach-gcc at cs dot stanford.edu
2023-04-21 18:00 ` cvs-commit at gcc dot gnu.org [this message]
2023-04-21 18:01 ` ktkachov at gcc dot gnu.org
2023-06-13 9:17 ` cvs-commit at gcc dot gnu.org
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