From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 2A7713857C55; Thu, 16 Feb 2023 18:14:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2A7713857C55 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1676571264; bh=91+EII6Bwhkhw4L6fS9+WVCCATAyWvIBnmF8rf//T4Y=; h=From:To:Subject:Date:In-Reply-To:References:From; b=uuYaKC2qiofwUvPoNtUMSyU7WPUBfyreftdcNk9D9aoYO7E6C0pEdYMHJfambDIv5 LnSQhpZkmkDVqdPNKPV9OxjPOGUNJuZsE85vS7f+AG1GLJeX4WY0c/EZXtYDuIwQH7 KVLAdSQ3ledbmsHORp2G5hLq+c8O95s8/4EXJ5M8= From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/108803] [10/11/12/13 Regression] wrong code for 128bit rotate on aarch64-unknown-linux-gnu with -Og Date: Thu, 16 Feb 2023 18:14:24 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 10.5 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108803 --- Comment #4 from Jakub Jelinek --- On the other side, if we knew that the backend would use something like the shifts with masking, we could then avoid the extra reverse unsigned shift b= y 1 + reverse unsigned shift by (63 - op1) & 63 plus two shifts by op1 & 63 and could do instead a single shift by -op1 & 63 (plus as before two shifts by = op1 & 63). So replace the current problematic code for foo in #c2 with: subs w5, w2, #64 lsl x6, x0, x5 - lsr x3, x0, 1 - mov w4, 63 - sub w4, w4, w2 - lsr x3, x3, x4 + neg w4, w2 + lsr x3, x0, x4 lsl x1, x1, x2 orr x1, x3, x1 lsl x0, x0, x2 csel x0, xzr, x0, pl csel x1, x6, x1, pl ret=