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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/108826] Inefficient address generation on
 POWER and RISC-V
Date: Thu, 16 Feb 2023 18:25:20 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108826

--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to palmer from comment #5)
> We've run into a handful of things that look like this before, I'm not su=
re
> if it's a backend issue or something more general.  There's two patterns
> here that are frequently bad on RISC-V: "unsigned int" array indices and
> unsigned int shifting.  I think they might both boil down to some problems
> we have tracking the high parts of registers around ABI boundaries.

That seems unrelated to the issue here. In this case the shift is in DI
(ptrmode) mode already so the shift is fine. See comment # 4 for the RTL (t=
his
was the RTL even for RV64).=