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From: "palmer at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/108826] Inefficient address generation on
 POWER and RISC-V
Date: Thu, 16 Feb 2023 18:21:10 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108826

--- Comment #5 from palmer at gcc dot gnu.org ---
We've run into a handful of things that look like this before, I'm not sure=
 if
it's a backend issue or something more general.  There's two patterns here =
that
are frequently bad on RISC-V: "unsigned int" array indices and unsigned int
shifting.  I think they might both boil down to some problems we have track=
ing
the high parts of registers around ABI boundaries.

FWIW, the smallest bad code I can get is

    unsigned int func(unsigned int ui) {
        return (ui >> 6 & 5) << 2;
    }

    func:
        srliw   a0,a0,6
        slliw   a0,a0,2
        andi    a0,a0,20
        ret

which is particularly awkward as enough is going right to try and move that
andi, but we still end up with the double shifts.=