From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 274A3385771B; Wed, 19 Apr 2023 08:35:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 274A3385771B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681893354; bh=iGpro7V/0+LlAypIoWeyhqJcWI8EcJHo8jJKo2Vf31c=; h=From:To:Subject:Date:In-Reply-To:References:From; b=BRo8536SH1FNwK824Xx95kk9L0OVSWMEa/JwT2D4aXcO+VuVAenrPvJ/cOfTUDYLb ZY7LUaeWt20msLJhE/EDVFDuSYPb97eFuaDuCLwAAofBwszoiEZVuD3T6XuGwsi8yK EEKbFQ2k/eLmGs4r1EZDaa1MuuCgENFaa3+ZfXio= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/108840] Aarch64 doesn't optimize away shift counter masking Date: Wed, 19 Apr 2023 08:35:50 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: ktkachov at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108840 --- Comment #4 from CVS Commits --- The master branch has been updated by Kyrylo Tkachov : https://gcc.gnu.org/g:136330bf637b50a4f10ace017a4316541386b9c0 commit r14-62-g136330bf637b50a4f10ace017a4316541386b9c0 Author: Kyrylo Tkachov Date: Wed Apr 19 09:34:40 2023 +0100 aarch64: PR target/108840 Simplify register shift RTX costs and elimina= te shift amount masking In this PR we fail to eliminate explicit &31 operations for variable sh= ifts such as in: void bar (int x[3], int y) { x[0] <<=3D (y & 31); x[1] <<=3D (y & 31); x[2] <<=3D (y & 31); } This is rejected by RTX costs that end up giving too high a cost for: (set (reg:SI 96) (ashift:SI (reg:SI 98) (subreg:QI (and:SI (reg:SI 99) (const_int 31 [0x1f])) 0))) There is code to handle the AND-31 case in rtx costs, but it gets confu= sed by the subreg. It's easy enough to fix by looking inside the subreg when costing the expression. While doing that I noticed that the ASHIFT case and the other shift-like cases are almost identical and we should just merge them. This code will only be used for valid in= sns anyway, so the code after this patch should do the Right Thing (TM) for all such shift cases. With this patch there are no more "and wn, wn, 31" instructions left in= the testcase. Bootstrapped and tested on aarch64-none-linux-gnu. PR target/108840 gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_rtx_costs): Merge ASHIFT a= nd ROTATE, ROTATERT, LSHIFTRT, ASHIFTRT cases. Handle subregs in = op1. gcc/testsuite/ChangeLog: * gcc.target/aarch64/pr108840.c: New test.=