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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug libgcc/108891] libatomic: AArch64 SEQ_CST 16-byte load missing
 barrier
Date: Fri, 24 Mar 2023 16:51:48 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108891

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Wilco Dijkstra <wilco@gcc.gnu.org>:

https://gcc.gnu.org/g:1f641d6aba284e0c277e6684cd6b2c73591cd14d

commit r13-6855-g1f641d6aba284e0c277e6684cd6b2c73591cd14d
Author: Wilco Dijkstra <wilco.dijkstra@arm.com>
Date:   Fri Feb 10 17:41:05 2023 +0000

    libatomic: Fix SEQ_CST 128-bit atomic load [PR108891]

    The LSE2 ifunc for 16-byte atomic load requires a barrier before the LD=
P -
    without it, it effectively has Load-AcquirePC semantics similar to LDAP=
R,
    which is less restrictive than what __ATOMIC_SEQ_CST requires.  This pa=
tch
    fixes this and adds comments to make it easier to see which sequence is
    used for each case.  Use a load/store exclusive loop for store to simpl=
ify
    testing memory ordering is correct (it is slightly faster too).

    libatomic/
            PR libgcc/108891
            * config/linux/aarch64/atomic_16.S: Fix libat_load_16_i1.
            Add comments describing the memory order.=