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From: "wilco at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug libgcc/108891] New: libatomic: AArch64 SEQ_CST 16-byte load
 missing barrier
Date: Wed, 22 Feb 2023 18:48:15 +0000
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X-Bugzilla-Product: gcc
X-Bugzilla-Component: libgcc
X-Bugzilla-Version: 13.0
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108891

            Bug ID: 108891
           Summary: libatomic: AArch64 SEQ_CST 16-byte load missing
                    barrier
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: libgcc
          Assignee: unassigned at gcc dot gnu.org
          Reporter: wilco at gcc dot gnu.org
  Target Milestone: ---

LSE2 uses the following sequence for a 16-byte atomic load:

ldp     res0, res1, [x0]
dmb     ish

The AArch64 memory model allows the LDP to be reordered with an earlier STL=
XP
(eg. a SEQ_CST exchange), thus breaking SEQ_CST ordering.

To avoid this, atomic loads need a barrier before the LDP - either DBM ISHL=
D or
LDAR works.=