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From: "meissner at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/108958] New: Powerpcle could generate mtvsrdd for zero
 extend DI to TI mode, when the TImode is in a vector register
Date: Mon, 27 Feb 2023 22:28:49 +0000
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X-Bugzilla-Type: new
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X-Bugzilla-Product: gcc
X-Bugzilla-Component: target
X-Bugzilla-Version: 13.0
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X-Bugzilla-Severity: enhancement
X-Bugzilla-Who: meissner at gcc dot gnu.org
X-Bugzilla-Status: UNCONFIRMED
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X-Bugzilla-Priority: P3
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D108958

            Bug ID: 108958
           Summary: Powerpcle could generate mtvsrdd for zero extend DI to
                    TI mode, when the TImode is in a vector register
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Severity: enhancement
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: meissner at gcc dot gnu.org
  Target Milestone: ---

If you have a DImode variable (i.e. long) in a GPR, and you want to zero ex=
tend
it to TImode (i.e. `__int128', and the result is needed in a vector registe=
r,
you could just do a single `mtvsrdd' instruction, instead of separate zero a
GPR register, and then `mtvsrd' and `mtvsrdd' instructions.=