[Bug rtl-optimization/109035] meaningless memory store on RISC-V and LoongArch

["chenglulu at loongson dot cn" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109035

--- Comment #6 from chenglulu <chenglulu at loongson dot cn> ---
I tried changing the code,
diff --git a/gcc/lra-eliminations.cc b/gcc/lra-eliminations.cc
index 42206366669..efaea6922b5 100644
--- a/gcc/lra-eliminations.cc
+++ b/gcc/lra-eliminations.cc
@@ -914,6 +914,11 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p,
bool first_p,
       /* First see if the source is of the form (plus (...) CST).  */
       if (plus_src && poly_int_rtx_p (XEXP (plus_src, 1), &offset))
        plus_cst_src = plus_src;
+      else if (plus_src && ira_reg_equiv[REGNO (XEXP (plus_src, 1))].constant)
+       {
+         poly_int_rtx_p (ira_reg_equiv[REGNO (XEXP (plus_src, 1))].constant,
&offset);
+         plus_cst_src = gen_rtx_PLUS (GET_MODE (XEXP (plus_src, 0)),XEXP
(plus_src, 0), ira_reg_equiv[REGNO (XEXP (plus_src, 1))].constant);
+       }
       /* Check that the first operand of the PLUS is a hard reg or
         the lowpart subreg of one.  */
       if (plus_cst_src)

Redundant instructions can be eliminated, but I don't know if it can be
modified like this.