[Bug target/109040] [13 Regression] wrong code with v16hi compare & mask on riscv64 at -O2 since r13-4907-g2e886eef7f2b5a

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109040

--- Comment #9 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:9d1a6119590ef828f9782a7083d03e535bc2f2cf

commit r13-7178-g9d1a6119590ef828f9782a7083d03e535bc2f2cf
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Fri Apr 14 09:20:49 2023 +0200

    combine: Fix AND handling for WORD_REGISTER_OPERATIONS targets [PR109040]

    The following testcase is miscompiled on riscv since the addition
    of *mvconst_internal define_insn_and_split.
    We have:
    (insn 36 35 39 2 (set (mem/c:SI (plus:SI (reg/f:SI 65 frame)
                    (const_int -64 [0xffffffffffffffc0])) [2  S4 A128])
            (reg:SI 166)) "pr109040.c":9:11 178 {*movsi_internal}
         (expr_list:REG_DEAD (reg:SI 166)
            (nil)))
    (insn 39 36 40 2 (set (reg:SI 171)
            (zero_extend:SI (mem/c:HI (plus:SI (reg/f:SI 65 frame)
                        (const_int -64 [0xffffffffffffffc0])) [0  S2 A128])))
"pr109040.c":9:11 111 {*zero_extendhisi2}
         (nil))
    and RTL DSE's replace_read since r0-86337-g18b526e806ab6455 handles
    even different modes like in the above case, and so it optimizes it into:
    (insn 47 35 39 2 (set (reg:HI 175)
            (subreg:HI (reg:SI 166) 0)) "pr109040.c":9:11 179 {*movhi_internal}
         (expr_list:REG_DEAD (reg:SI 166)
            (nil)))
    (insn 39 47 40 2 (set (reg:SI 171)
            (zero_extend:SI (reg:HI 175))) "pr109040.c":9:11 111
{*zero_extendhisi2}
         (expr_list:REG_DEAD (reg:HI 175)
            (nil)))
    Pseudo 166 is result of AND with 0x8084c constant (forced into a register).
    Combine attempts to combine the AND with the insn 47 above created by DSE,
    and turns it because of WORD_REGISTER_OPERATIONS and its assumption that
all
    the subword operations are actually done on word mode into:
    (set (subreg:SI (reg:HI 175) 0)
        (and:SI (reg:SI 167 [ m ])
            (reg:SI 168)))
    and later on the ZERO_EXTEND is thrown away.

    We then see
    (and:SI (subreg:SI (reg:HI 175) 0) (const_int 0x84c))
    and optimize that into
    (subreg:SI (and:HI (reg:HI 175) (const_int 0x84c)) 0)
    which is still fine, in WORD_REGISTER_OPERATIONS the AND in HImode
    will set all upper bits up to BITS_PER_WORD to zeros.

    But later on simplify_binary_operation_1 or simplify_and_const_int_1
    sees that because nonzero_bits ((reg:HI 175), HImode) == 0x84c, we can
    optimize the AND into (reg:HI 175).  That isn't correct, because while
    the low 16 bits of that REG are known to have all bits but 0x84c cleared,
    we don't know that all the upper 16 bits are all clear as well.
    So, for WORD_REGISTER_OPERATIONS for integral modes smaller than word mode,
    we need to check all bits from word_mode in nonzero_bits for the
optimizations.

    2023-04-14  Jeff Law  <jlaw@ventanamicro.com>
                Jakub Jelinek  <jakub@redhat.com>

            PR target/108947
            PR target/109040
            * combine.cc (simplify_and_const_int_1): Compute nonzero_bits in
            word_mode rather than mode if WORD_REGISTER_OPERATIONS and mode is
            smaller than word_mode.
            * simplify-rtx.cc (simplify_context::simplify_binary_operation_1)
            <case AND>: Likewise.

            * gcc.dg/pr108947.c: New test.
            * gcc.c-torture/execute/pr109040.c: New test.