From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 5D72D3858CDB; Thu, 9 Mar 2023 10:21:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5D72D3858CDB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1678357270; bh=7RagV8ZmZJm7pZi1KyeH2p+0QhjIc59bxUZdu+NoaOY=; h=From:To:Subject:Date:From; b=rVIv3cMC4l+cXmPd/5sMSzCegBJpcouc0KbOcBvglvXLfWs4b/AzzlgSXWuQLvlka mmLZjgxVdVu/OLN3kN1pzWHnbHYsLdROoXk0n6hFgaKqRIaRFSF9+jXq6dQEPJJVnY z+8lx1/l1RWwAuMJ+0Qq6pC65mgOuTcNFbrLcD3c= From: "dorazzsoft at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/109078] New: Missing optimization on aarch64 for types like `float32x4x2_t` Date: Thu, 09 Mar 2023 10:21:09 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.2.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: dorazzsoft at gmail dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter target_milestone Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109078 Bug ID: 109078 Summary: Missing optimization on aarch64 for types like `float32x4x2_t` Product: gcc Version: 12.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: dorazzsoft at gmail dot com Target Milestone: --- Here is a simple code: https://godbolt.org/z/3qMTTfcfx #include #include #include void simple_gemm( float* restrict out, float const* restrict a, float const* restrict b, size_t k, bool zero_out ) { register float32x4x2_t o0; o0.val[0] =3D vdupq_n_f32(0.0f); o0.val[1] =3D vdupq_n_f32(0.0f); // begin dot { register float32x4_t a0; register float32x4x2_t b0; while (k >=3D 1) { b0 =3D vld1q_f32_x2(b); a0 =3D vdupq_n_f32(a[0]); o0.val[0] =3D vfmaq_f32(o0.val[0], a0, b0.val[0]); o0.val[1] =3D vfmaq_f32(o0.val[1], a0, b0.val[1]); b +=3D 8; a +=3D 1; k -=3D 1; } } // end dot // begin writeback { if (!zero_out) { register float32x4x2_t t0; t0 =3D vld1q_f32_x2(out); o0.val[0] =3D vaddq_f32(o0.val[0], t0.val[0]); o0.val[1] =3D vaddq_f32(o0.val[1], t0.val[1]); } // TODO: both clang and gcc generates redundant mov because of bad regi= ster allocation. vst1q_f32_x2(out, o0); } // end writeback } The assembly generated: simple_gemm: movi v3.4s, 0 and w4, w4, 255 mov v4.16b, v3.16b cbz x3, .L2 .L3: ld1 {v0.4s - v1.4s}, [x2], 32 subs x3, x3, #1 ld1r {v2.4s}, [x1], 4 fmla v3.4s, v2.4s, v0.4s fmla v4.4s, v2.4s, v1.4s bne .L3 .L2: cbnz w4, .L4 ld1 {v0.4s - v1.4s}, [x0] fadd v3.4s, v3.4s, v0.4s fadd v4.4s, v4.4s, v1.4s .L4: mov v0.16b, v3.16b mov v1.16b, v4.16b st1 {v0.4s - v1.4s}, [x0] ret The two values of float32x4x2_t o0 are assigned to v3 and v4. They should be able to be used directly as operands of st1, so the mov at L4 is redundant.= =20=20 I also found that in some code, the register pair may not be neighboring, w= hich results in some redundant mov instructions.=