From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id A310B3858C5E; Thu, 9 Mar 2023 22:20:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A310B3858C5E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1678400426; bh=7DOdNpNBrzDkGF9lUUrzJl1PqoVKJooT88aNq/QYJjg=; h=From:To:Subject:Date:In-Reply-To:References:From; b=wByxjd3TSFaxyI0UTY/4ugUNrWWt0VBrMHfwdSzB1qvs0BnsW0YC71L+hc3utQBBb 14/BiqWgxp02oZN9KlK/6W1N6mL8+TUFb48ja5sIRkw21YIiq8PFoFpyamKk7Lzr7T 9TCL7uXGtoDDaFOL/+v8fyjn2Lj6cDqZxVnxWxFs= From: "ubizjak at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/109079] Missing optimization for x86 avx intrinsic _mm256_zeroall(). Date: Thu, 09 Mar 2023 22:20:26 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 12.2.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: ubizjak at gmail dot com X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: component Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109079 Uro=C5=A1 Bizjak changed: What |Removed |Added ---------------------------------------------------------------------------- Component|target |rtl-optimization --- Comment #2 from Uro=C5=A1 Bizjak --- (In reply to Richard Biener from comment #1) > I think it wasn't intended to be used this way, but sure. Currently it's= a > black-box in the target I think and so nothing sees the redundancy. _mm256_zeroall is emitted as: (insn 6 3 7 2 (parallel [ (unspec_volatile [ (const_int 0 [0]) ] UNSPECV_VZEROALL) (set (reg:V8SI 20 xmm0) (const_vector:V8SI [ (const_int 0 [0]) repeated x8 ])) (set (reg:V8SI 21 xmm1) (const_vector:V8SI [ (const_int 0 [0]) repeated x8 ])) ... (set (reg:V8SI 51 xmm15) (const_vector:V8SI [ (const_int 0 [0]) repeated x8 ])) ]) and _mm256_setzero_ps as: (insn 7 6 8 2 (set (reg:V8SF 83) (const_vector:V8SF [ (const_double:SF 0.0 [0x0.0p+0]) repeated x8 ])) There is mode mismatch between (insn 6) and (insn 7) so postreload CSE is n= ot able to eliminate (insn 7). Using the following patch^w hack that changes the mode of vzeroall register= s: --cut here-- diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index b4d9ab40ab9..cf15ca8f611 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1737,9 +1737,9 @@ (define_predicate "vzeroall_operation" if (GET_CODE (elt) !=3D SET || GET_CODE (SET_DEST (elt)) !=3D REG - || GET_MODE (SET_DEST (elt)) !=3D V8SImode + || GET_MODE (SET_DEST (elt)) !=3D V8SFmode || REGNO (SET_DEST (elt)) !=3D GET_SSE_REGNO (i) - || SET_SRC (elt) !=3D CONST0_RTX (V8SImode)) + || SET_SRC (elt) !=3D CONST0_RTX (V8SFmode)) return false; } return true; diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 172ec3bea4f..81e02086606 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -25244,8 +25244,8 @@ (define_expand "avx_vzeroall" for (regno =3D 0; regno < nregs; regno++) XVECEXP (operands[0], 0, regno + 1) - =3D gen_rtx_SET (gen_rtx_REG (V8SImode, GET_SSE_REGNO (regno)), - CONST0_RTX (V8SImode)); + =3D gen_rtx_SET (gen_rtx_REG (V8SFmode, GET_SSE_REGNO (regno)), + CONST0_RTX (V8SFmode)); }) (define_insn "*avx_vzeroall" --cut here-- the compiler is able to eliminate (insn 7) in postreload pass, producing: fn: vzeroall vmovups %ymm0, (%rdi) vzeroupper ret It looks to me that postreload CSE should be taught about the equivalence of vector modes - a V8SFmode zero has the same bit representation as V8SImode = zero (and V4DImode, ...), as long as the mode size is the same. Recategorizing as rtl-optimization.=