From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 3EE083858414; Mon, 13 Mar 2023 17:01:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3EE083858414 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1678726898; bh=9kc2fBzBAKDj2JkHSLliJU+7YQjiGPVRwLu/r47cyQ0=; h=From:To:Subject:Date:In-Reply-To:References:From; b=ejn4AVOVixF4TfWf22tIoKz3NoRqU8RsDG4+bjjPdHsLij1tJMkW7CmxF2I0rRF84 Qwi9bNTq1IhnHymxX8X5dqCmqa+/yHjfn2Fmp/xlZocttHEdN1dABuWjSUKlAtWWHE GRLnpiB7Y5pZaGvvPnWcQ/7SfhLiNzb05uB/DDKM= From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64 Date: Mon, 13 Mar 2023 17:01:37 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: build, ice-checking, ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P1 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 13.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109092 Jakub Jelinek changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |jakub at gcc dot gnu.org, | |law at gcc dot gnu.org --- Comment #3 from Jakub Jelinek --- In this case that would be certainly better, because if the intent is to ne= ver match for=20 move from vl register, then even subreg of vl would be a vl register and so= if it punted just on moves from vl REG and not SUBREG thereof, after reload it could get vl REG from the SUBREG and fail at that point. Note, *zero_extendsidi2_internal uses the #c1 way...=