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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/109092] [13 Regression] ICE: RTL check: expected code
 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on
 riscv64
Date: Tue, 14 Mar 2023 18:30:37 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109092

--- Comment #5 from Uro=C5=A1 Bizjak <ubizjak at gmail dot com> ---
(In reply to Uro=C5=A1 Bizjak from comment #2)
> (In reply to Andrew Pinski from comment #1)
>=20
> > The issue is register_operand accepts subreg but then REGNO is checked =
on it.
> > That is obviously wrong. It should be "REG_P (operands[1]) && REGNO
> > (operands[1]) =3D=3D VL_REGNUM" instead ...
>=20
> reg_or_subregno is better.

However, please note that reg_or_subregno asserts that we always have SUBRE=
G of
REG:

unsigned int
reg_or_subregno (const_rtx reg)
{
  if (GET_CODE (reg) =3D=3D SUBREG)
    reg =3D SUBREG_REG (reg);
  gcc_assert (REG_P (reg));
  return REGNO (reg);
}

but before reload register_operand allows SUBREG of MEM:

bool
register_operand (rtx op, machine_mode mode)
{
  if (GET_CODE (op) =3D=3D SUBREG)
    {
      rtx sub =3D SUBREG_REG (op);

      /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
         because it is guaranteed to be reloaded into one.
         Just make sure the MEM is valid in itself.
         (Ideally, (SUBREG (MEM)...) should not exist after reload,
         but currently it does result from (SUBREG (REG)...) where the
         reg went on the stack.)  */
      if (!REG_P (sub) && (reload_completed || !MEM_P (sub)))
        return false;
    }
  else if (!REG_P (op))
    return false;
  return general_operand (op, mode);
}

OTOH, we do have:

rtlanal.h:const unsigned int MEM_REGNO =3D ~0U;

which implies that it is possible to get a REGNO of a MEM, so perhaps the
assert in reg_or_subregno is too strict.=