[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:40fc8e3d4f600d89e6b065d6f12db7a816269c8f

commit r13-7138-g40fc8e3d4f600d89e6b065d6f12db7a816269c8f
Author: Yanzhang Wang <yanzhang.wang@intel.com>
Date:   Tue Apr 11 19:37:48 2023 +0800

    RISC-V: Fix regression of -fzero-call-used-regs=all [PR109104]

    This patch registers a riscv specific function to
    TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
    clean gpr and vector relevant registers.

    gcc/ChangeLog:

            PR target/109104
            * config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl): New.
            * config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl): New.
            (emit_vlmax_vsetvl): Use emit_hard_vlmax_vsetvl.
            * config/riscv/riscv.cc (vector_zero_call_used_regs): New.
            (riscv_zero_call_used_regs): New.
            (TARGET_ZERO_CALL_USED_REGS): New.

    gcc/testsuite/ChangeLog:

            PR target/109104
            * gcc.target/riscv/zero-scratch-regs-1.c: New test.
            * gcc.target/riscv/zero-scratch-regs-2.c: New test.
            * gcc.target/riscv/zero-scratch-regs-3.c: New test.

    Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
    Co-authored-by: Pan Li <pan2.li@intel.com>
    Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
    Co-authored-by: Kito Cheng <kito.cheng@sifive.com>