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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at
 emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv
Date: Tue, 14 Mar 2023 08:49:38 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109104

--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Roger Sayle from comment #1)
> Not exactly my area of expertise, but adding
>=20
>   if (!can_create_pseudo_p ())
>     return false;
>=20
> at the start of legitimize_move on line 262 of riscv-v.cc should help.
> Other solutions include clearing a vector register without requiring
> a scalar register (to set the vector length) by xoring it with itself,
> or possibly providing a riscv backend target hook to override the default
> default_zero_call_used_regs implementation.
>=20
> If the vector length can be set to zero, that might be an alternative
> to clearing call-used vector registers.

We (me && kito) are trying to find the solution to fix it.
Actually, xoring itself can not help since vxor.vv also needs=20
vsetvl a5,zero.... Setting vector-length to be VLMAX.

We don't have an instruction in RVV ISA can zero a whole vector register
without
vsetvl to setting VLMAX vector-length.

I think maybe Kito knows how to fix it.

We will definetely fix it soon in GCC 13.

Thanks.=