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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/109406] Missing use of aarch64 SVE2 unpredicated integer
 multiply
Date: Mon, 24 Apr 2023 09:28:52 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109406

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:9fd4a38c2f30b72ad5e3df7acb1ade201d8ac2cd

commit r14-193-g9fd4a38c2f30b72ad5e3df7acb1ade201d8ac2cd
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Mon Apr 24 10:27:31 2023 +0100

    aarch64: PR target/109406 Add support for SVE2 unpredicated MUL

    SVE2 supports an unpredicated vector integer MUL form that we can emit =
from
our SVE expanders
    without using up a predicate registers. This patch does so.
    As the SVE MUL expansion currently is templated away through a code
iterator I did not split it
    off just for this case but instead special-cased it in the define_expan=
d.
It seemed somewhat less
    invasive than the alternatives but I could split it off more explicitly=
 if
others want to.
    The div-by-bitmask_1.c testcase is adjusted to expect this new MUL form.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/ChangeLog:

            PR target/109406
            * config/aarch64/aarch64-sve.md (<optab><mode>3): Handle
TARGET_SVE2 MUL
            case.
            * config/aarch64/aarch64-sve2.md
(*aarch64_mul_unpredicated_<mode>): New
            pattern.

    gcc/testsuite/ChangeLog:

            PR target/109406
            * gcc.target/aarch64/sve2/div-by-bitmask_1.c: Adjust for
unpredicated SVE2
            MUL.
            * gcc.target/aarch64/sve2/unpred_mul_1.c: New test.=