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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/109479] [RISC-V] Build vint64m1_t with
 rv64gc_zve32x_zvl64b should promote information like "vint64m1_t requires the
 'zve64x' extensions"
Date: Wed, 12 Apr 2023 15:08:38 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109479

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:31eb8f18bbe64613fd8d77c4520c00beeb13598f

commit r13-7156-g31eb8f18bbe64613fd8d77c4520c00beeb13598f
Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Date:   Wed Apr 12 21:56:05 2023 +0800

    RISC-V: Fix supporting data type according to RVV ISA. [PR109479]

    For vint64m*_t, we should only allow them in zve64* instead of
zve32*_zvl64b (>=3D64b).
    Ideally, we should make error message more friendly like Clang.
    https://godbolt.org/z/f9GMv4dMo to report the RVV type require extensti=
on
name.
    However, I failed to find a way to do that. So current GCC can only rep=
ort
"unknown" type.
    And I added comments to remind us doing this in the future.

    gcc/ChangeLog:

            PR target/109479
            * config/riscv/riscv-vector-builtins-types.def (vint8mf8_t): Fix
predicate.
            (vint16mf4_t): Ditto.
            (vint32mf2_t): Ditto.
            (vint64m1_t): Ditto.
            (vint64m2_t): Ditto.
            (vint64m4_t): Ditto.
            (vint64m8_t): Ditto.
            (vuint8mf8_t): Ditto.
            (vuint16mf4_t): Ditto.
            (vuint32mf2_t): Ditto.
            (vuint64m1_t): Ditto.
            (vuint64m2_t): Ditto.
            (vuint64m4_t): Ditto.
            (vuint64m8_t): Ditto.
            (vfloat32mf2_t): Ditto.
            (vbool64_t): Ditto.
            * config/riscv/riscv-vector-builtins.cc (register_builtin_type):
Add comments.
            (register_vector_type): Ditto.
            (check_required_extensions): Fix condition.
            * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ZVE64): Rem=
ove
it.
            (RVV_REQUIRE_ELEN_64): New define.
            (RVV_REQUIRE_MIN_VLEN_64): Ditto.
            * config/riscv/riscv-vector-switch.def (TARGET_VECTOR_FP32): Re=
move
it.
            (TARGET_VECTOR_FP64): Ditto.
            (ENTRY): Fix predicate.
            * config/riscv/vector-iterators.md: Fix predicate.

    gcc/testsuite/ChangeLog:

            PR target/109479
            * gcc.target/riscv/rvv/base/pr109479-1.c: New test.
            * gcc.target/riscv/rvv/base/pr109479-2.c: New test.
            * gcc.target/riscv/rvv/base/pr109479-3.c: New test.
            * gcc.target/riscv/rvv/base/pr109479-4.c: New test.
            * gcc.target/riscv/rvv/base/pr109479-5.c: New test.
            * gcc.target/riscv/rvv/base/pr109479-6.c: New test.=