[Bug target/109508] New: [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64

[Bug target/109508] New: [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508

            Bug ID: 109508
           Summary: [13 Regression] ICE: in extract_insn, at recog.cc:2791
                    with -mcpu=sifive-s76 on riscv64
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zsojka at seznam dot cz
  Target Milestone: ---
              Host: x86_64-pc-linux-gnu
            Target: riscv64-unknown-linux-gnu

Created attachment 54855
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54855&action=edit
reduced testcase

Compiler output:
$ riscv64-unknown-linux-gnu-gcc -mcpu=sifive-s76 testcase.c
testcase.c: In function 'foo':
testcase.c:9:1: error: unrecognizable insn:
    9 | }
      | ^
(insn 16 15 17 2 (set (reg:DI 146)
        (if_then_else:DI (ne:DI (reg:DI 147)
                (const_int 0 [0]))
            (const_int 0 [0])
            (const_int 6 [0x6]))) -1
     (nil))
during RTL pass: vregs
testcase.c:9:1: internal compiler error: in extract_insn, at recog.cc:2791
0x7a1b18 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /repo/gcc-trunk/gcc/rtl-error.cc:108
0x7a1b94 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        /repo/gcc-trunk/gcc/rtl-error.cc:116
0x7932ca extract_insn(rtx_insn*)
        /repo/gcc-trunk/gcc/recog.cc:2791
0xd1ae6f instantiate_virtual_regs_in_insn
        /repo/gcc-trunk/gcc/function.cc:1611
0xd1ae6f instantiate_virtual_regs
        /repo/gcc-trunk/gcc/function.cc:1985
0xd1ae6f execute
        /repo/gcc-trunk/gcc/function.cc:2034
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

$ riscv64-unknown-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=/repo/gcc-trunk/binary-latest-riscv64/bin/riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/repo/gcc-trunk/binary-trunk-r13-7168-20230413170248-ga1afdc6e2aa-checking-yes-rtl-df-extra-riscv64/bin/../libexec/gcc/riscv64-unknown-linux-gnu/13.0.1/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /repo/gcc-trunk//configure --enable-languages=c,c++
--enable-valgrind-annotations --disable-nls --enable-checking=yes,rtl,df,extra
--with-cloog --with-ppl --with-isl --with-isa-spec=2.2
--with-sysroot=/usr/riscv64-unknown-linux-gnu --build=x86_64-pc-linux-gnu
--host=x86_64-pc-linux-gnu --target=riscv64-unknown-linux-gnu
--with-ld=/usr/bin/riscv64-unknown-linux-gnu-ld
--with-as=/usr/bin/riscv64-unknown-linux-gnu-as --disable-multilib
--disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-r13-7168-20230413170248-ga1afdc6e2aa-checking-yes-rtl-df-extra-riscv64
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 13.0.1 20230413 (experimental) (GCC)

[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2023-04-14
             Status|UNCONFIRMED                 |NEW

[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |law at gcc dot gnu.org
           Priority|P3                          |P4

--- Comment #1 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Trivial issue in the riscv backend.  We just need to fix the operand on the
movXXcc pattern.

[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |13.0

[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED

[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:a647198fcf7463a42c8e035a429200e7998735dc

commit r13-7198-ga647198fcf7463a42c8e035a429200e7998735dc
Author: Jeff Law <jlaw@ventanamicro>
Date:   Sun Apr 16 09:55:32 2023 -0600

    [committed] [PR target/109508] Adjust conditional move expansion for SFB

    Recently the conditional move expander's predicates were loosened for the
    benefit of the THEAD processors.  In particular one operand that was
    previously "register_operand" is now "reg_or_0_operand".  That's fine for
    THEAD, but breaks for SFB which requires a register for that operand.

    This results in an ICE when compiling the testcase an SFB target such as
    the sifive s76.

    This change adjusts the expansion code slightly to copy the value into
    a register for SFB.

    Bootstrapped and regression tested (c,c++,fortran only) with a toolchain
    configured to enable SFB by default.

            PR target/109508
    gcc/

            * config/riscv/riscv.cc (riscv_expand_conditional_move): For
            TARGET_SFB_ALU, force the true arm into a register.

    gcc/testsuite
            * gcc.target/riscv/pr109508.c: New test.

[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|ASSIGNED                    |RESOLVED

--- Comment #3 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Fixed on the trunk.