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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/109508] [13 Regression] ICE: in extract_insn, at
 recog.cc:2791 with -mcpu=sifive-s76 on riscv64
Date: Sun, 16 Apr 2023 15:56:40 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109508

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:a647198fcf7463a42c8e035a429200e7998735dc

commit r13-7198-ga647198fcf7463a42c8e035a429200e7998735dc
Author: Jeff Law <jlaw@ventanamicro>
Date:   Sun Apr 16 09:55:32 2023 -0600

    [committed] [PR target/109508] Adjust conditional move expansion for SFB

    Recently the conditional move expander's predicates were loosened for t=
he
    benefit of the THEAD processors.  In particular one operand that was
    previously "register_operand" is now "reg_or_0_operand".  That's fine f=
or
    THEAD, but breaks for SFB which requires a register for that operand.

    This results in an ICE when compiling the testcase an SFB target such as
    the sifive s76.

    This change adjusts the expansion code slightly to copy the value into
    a register for SFB.

    Bootstrapped and regression tested (c,c++,fortran only) with a toolchain
    configured to enable SFB by default.

            PR target/109508
    gcc/

            * config/riscv/riscv.cc (riscv_expand_conditional_move): For
            TARGET_SFB_ALU, force the true arm into a register.

    gcc/testsuite
            * gcc.target/riscv/pr109508.c: New test.=