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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/109615] Redundant VSETVL after optimized code of RVV Date: Fri, 05 May 2023 13:18:36 +0000 [thread overview] Message-ID: <bug-109615-4-3rxkf0Tmz5@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-109615-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109615 --- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>: https://gcc.gnu.org/g:d875d75653ed67e125e70dd8530182ce7872af65 commit r14-503-gd875d75653ed67e125e70dd8530182ce7872af65 Author: Juzhe-Zhong <juzhe.zhong@rivai.ai> Date: Fri May 5 14:33:44 2023 +0800 RISC-V: Fix PR109615 This patch is to fix following case: void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond) { size_t vl = 101; if (cond) vl = m * 2; else vl = m * 2 * vl; for (size_t i = 0; i < n; i++) { vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); __riscv_vse8_v_i8mf8 (out + i, v, vl); vbool64_t mask = __riscv_vlm_v_b64 (in + i + 100, vl); vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in + i + 100, vl); __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl); } for (size_t i = 0; i < n; i++) { vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl); __riscv_vse8_v_i8mf8 (out + i + 300, v, vl); } } The value of "vl" is coming from different blocks so it will be wrapped as a PHI node of each block. In the first loop, the "vl" source is a PHI node from bb 4. In the second loop, the "vl" source is a PHI node from bb 5. since bb 5 is dominated by bb 4, the PHI input of "vl" in the second loop is the PHI node of "vl" in bb 4. So when 2 "vl" PHI node are both degenerate PHI node (the phi->num_inputs () == 1) and their only input are same, it's safe for us to consider they are compatible. This patch is only optimize degenerate PHI since it's safe and simple optimization. non-dengerate PHI are considered as incompatible unless the PHI are the same in RTL_SSA. TODO: non-generate PHI is complicated, we can support it when it is necessary in the future. Before this patch: ... .L2: addi a4,a1,100 add t1,a0,a2 mv t0,a0 beq a2,zero,.L1 vsetvli zero,a3,e8,mf8,tu,mu .L4: addi a6,t0,100 addi a7,a4,-100 vle8.v v1,0(t0) addi t0,t0,1 vse8.v v1,0(a7) vlm.v v0,0(a6) vle8.v v1,0(a6),v0.t vse8.v v1,0(a4) addi a4,a4,1 bne t0,t1,.L4 addi a0,a0,300 addi a1,a1,300 add a2,a0,a2 vsetvli zero,a3,e8,mf8,ta,ma .L5: vle8.v v2,0(a0) addi a0,a0,1 vse8.v v2,0(a1) addi a1,a1,1 bne a2,a0,.L5 .L1: ret After this patch: ... .L2: addi a4,a1,100 add t1,a0,a2 mv t0,a0 beq a2,zero,.L1 vsetvli zero,a3,e8,mf8,tu,mu .L4: addi a6,t0,100 addi a7,a4,-100 vle8.v v1,0(t0) addi t0,t0,1 vse8.v v1,0(a7) vlm.v v0,0(a6) vle8.v v1,0(a6),v0.t vse8.v v1,0(a4) addi a4,a4,1 bne t0,t1,.L4 addi a0,a0,300 addi a1,a1,300 add a2,a0,a2 .L5: vle8.v v2,0(a0) addi a0,a0,1 vse8.v v2,0(a1) addi a1,a1,1 bne a2,a0,.L5 .L1: ret PR target/109615 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (avl_info::multiple_source_equal_p): Add denegrate PHI optmization. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/avl_single-74.c: Adapt testcase. * gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Ditto. * gcc.target/riscv/rvv/vsetvl/pr109615.c: New test.
next prev parent reply other threads:[~2023-05-05 13:18 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-25 1:07 [Bug c/109615] New: " pan2.li at intel dot com 2023-04-25 1:08 ` [Bug target/109615] " pinskia at gcc dot gnu.org 2023-05-05 13:18 ` cvs-commit at gcc dot gnu.org [this message] 2024-01-18 3:00 ` pan2.li at intel dot com 2024-01-20 17:23 ` pinskia at gcc dot gnu.org
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