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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/109617] RISC-V: ICE for vlmul_ext_v intrinsic API
Date: Tue, 02 May 2023 15:35:33 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109617

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:1adb1a653d6739589b12337c974c7e741cfb187c

commit r14-395-g1adb1a653d6739589b12337c974c7e741cfb187c
Author: Yanzhang Wang <yanzhang.wang@intel.com>
Date:   Wed Apr 26 21:06:02 2023 +0800

    RISC-V: ICE for vlmul_ext_v intrinsic API

            PR target/109617

    gcc/ChangeLog:

            * config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI w=
hen
MIN_VLEN >=3D 128.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.

    Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
    Co-authored-by: Pan Li <pan2.li@intel.com>
    Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>=