[Bug c/109617] New: RISC-V: ICE for vlmul_ext_v intrinsic API

[Bug c/109617] New: RISC-V: ICE for vlmul_ext_v intrinsic API

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109617

            Bug ID: 109617
           Summary: RISC-V: ICE for vlmul_ext_v intrinsic API
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pan2.li at intel dot com
  Target Milestone: ---

Given we have the bellow sample code.

#include <riscv_vector.h>

vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
  return __riscv_vlmul_ext_v_i16mf4_i16m8(op1);
}

It will have ICE when building with this option "riscv64-unknown-elf-gcc
-march=rv64gcv -O3 test.c -c -S -o -".

during RTL pass: expand
test.c: In function 'test_vlmul_ext_v_i16mf4_i16m8':
test.c:7:10: internal compiler error: in code_for_vlmul_extx32, at
./insn-opinit.h:572
    7 |   return __riscv_vlmul_ext_v_i16mf4_i16m8(op1);
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0x1c07559 code_for_vlmul_extx32(machine_mode)
        ./insn-opinit.h:572
0x1c0b14e riscv_vector::vlmul_ext::expand(riscv_vector::function_expander&)
const
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/config/riscv/riscv-vector-builtins-bases.cc:1522
0x1c03b2d riscv_vector::expand_builtin(unsigned int, tree_node*, rtx_def*)
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/config/riscv/riscv-vector-builtins.cc:3501
0x1bd8463 riscv_expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode,
int)
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/config/riscv/riscv-builtins.cc:379
0xe2951d expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode, int)
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/builtins.cc:7341
0x103cb67 expand_expr_real_1(tree_node*, rtx_def*, machine_mode,
expand_modifier, rtx_def**, bool)
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/expr.cc:11864
0x102e744 expand_expr_real(tree_node*, rtx_def*, machine_mode, expand_modifier,
rtx_def**, bool)
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/expr.cc:8999
0x1022e43 store_expr(tree_node*, rtx_def*, int, bool, bool)
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/expr.cc:6330
0x10213c1 expand_assignment(tree_node*, tree_node*, bool)
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/expr.cc:6048
0xe6cab9 expand_call_stmt
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/cfgexpand.cc:2829
0xe70886 expand_gimple_stmt_1
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/cfgexpand.cc:3880
0xe70f7a expand_gimple_stmt
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/cfgexpand.cc:4044
0xe79c1a expand_gimple_basic_block
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/cfgexpand.cc:6106
0xe7c17c execute
       
/home/pli/repos/toolchains/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc/cfgexpand.cc:6841

[Bug target/109617] RISC-V: ICE for vlmul_ext_v intrinsic API

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109617

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:1adb1a653d6739589b12337c974c7e741cfb187c

commit r14-395-g1adb1a653d6739589b12337c974c7e741cfb187c
Author: Yanzhang Wang <yanzhang.wang@intel.com>
Date:   Wed Apr 26 21:06:02 2023 +0800

    RISC-V: ICE for vlmul_ext_v intrinsic API

            PR target/109617

    gcc/ChangeLog:

            * config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when
MIN_VLEN >= 128.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.

    Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
    Co-authored-by: Pan Li <pan2.li@intel.com>
    Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>

[Bug target/109617] RISC-V: ICE for vlmul_ext_v intrinsic API

[kito at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109617

Kito Cheng <kito at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #2 from Kito Cheng <kito at gcc dot gnu.org> ---
fixed on trunk