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From: "ktkachov at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/109636] [14 Regression] ICE: in paradoxical_subreg_p, at
 rtl.h:3205 with -O -mcpu=a64fx
Date: Thu, 27 Apr 2023 08:26:04 +0000
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X-Bugzilla-Version: 14.0
X-Bugzilla-Keywords: ice-on-valid-code, needs-bisection
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109636

ktkachov at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2023-04-27
             Status|UNCONFIRMED                 |NEW
                 CC|                            |rsandifo at gcc dot gnu.org
     Ever confirmed|0                           |1

--- Comment #4 from ktkachov at gcc dot gnu.org ---
Confirmed. The operand that's blowing it up is:
(subreg:V2DI (reg/v:OI 97 [ w ]) 16)
at
rtx sve_op1 =3D simplify_gen_subreg (sve_mode, operands[1], <MODE>mode, 0);

simplify_gen_subreg, lowpart_subreg, copy_to_mode_reg and force_reg all ICE=
 :(=