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Subject: [Bug target/109636] [14 Regression] ICE: in paradoxical_subreg_p, at
 rtl.h:3205 with -O -march=armv8.4-a+sve
Date: Wed, 24 Jan 2024 15:58:51 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109636

--- Comment #12 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Tamar Christina <tnfchris@gcc.gnu.org=
>:

https://gcc.gnu.org/g:dfa17fd3b1a50cab51803e8a63c5c7b7db173523

commit r14-8394-gdfa17fd3b1a50cab51803e8a63c5c7b7db173523
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Wed Jan 24 15:58:34 2024 +0000

    AArch64: Fix expansion of Advanced SIMD div and mul using SVE [PR109636]

    As suggested in the ticket this replaces the expansion by converting the
    Advanced SIMD types to SVE types by simply printing out an SVE register=
 for
    these instructions.

    This fixes the subreg issues since there are no subregs involved anymor=
e.

    gcc/ChangeLog:

            PR target/109636
            * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
            mulv2di3): Remove.
            * config/aarch64/iterators.md (VQDIV): Remove.
            (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
            SVE_I_SIMD_DI): New.
            (VPRED, sve_lane_con): Add V4SI and V2DI.
            * config/aarch64/aarch64-sve.md (<optab><mode>3,
            @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
            (mul<mode>3): New, split from <optab><mode>3.
            (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
            * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
            *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
            SVE_FULL_HSDI_SIMD_DI.

    gcc/testsuite/ChangeLog:

            PR target/109636
            * gcc.target/aarch64/sve/pr109636_1.c: New test.
            * gcc.target/aarch64/sve/pr109636_2.c: New test.
            * gcc.target/aarch64/sve2/pr109636_1.c: New test.=